177 Commits

Author SHA1 Message Date
joachimschmidt557
f014de6456
stage2 ARM: fix debug info for arguments passed in registers 2022-09-20 17:14:31 +02:00
joachimschmidt557
258b058eec
stage2 ARM: make sub_sp_scratch MIR instruction use r4
r0 is used for argument passing, so this register is not available as
a scratch register upon function entry.
2022-09-20 17:14:27 +02:00
Andrew Kelley
bec70a1a39 stage2: remove pointless discards from source code
Good riddance!
2022-09-13 02:04:20 -07:00
joachimschmidt557
94499898e5
stage2 ARM: implement basic array_elem_val 2022-09-09 20:26:04 +02:00
joachimschmidt557
b976997e16
stage2 ARM: implement ptr_elem_val 2022-09-09 19:17:18 +02:00
joachimschmidt557
a0a7d15142
stage2 ARM: support larger function stacks
This is done by introducing a new Mir pseudo-instruction
2022-09-09 19:17:18 +02:00
joachimschmidt557
3794f2c493
stage2 ARM: implement struct_field_val for registers 2022-09-09 19:17:18 +02:00
joachimschmidt557
25729d6155
stage2 ARM: fix multiple uses of reuseOperand
- add missing checks whether destination fits into the operand
- remove reuseOperand invocations from airIsNullPtr and similar
  functions as we need to load the operands into temporary locations
2022-09-09 19:17:18 +02:00
joachimschmidt557
261fec8036
stage2 ARM: amend implementation of various AIR instructions
- unwrap_errunion_err for registers
- unwrap_errunion_payload for registers
- ptr_slice_len_ptr for all MCValues
- ptr_slice_ptr_ptr for all MCValues
2022-09-09 19:17:17 +02:00
joachimschmidt557
e2b029e2c8
stage2 ARM: implement field_parent_ptr 2022-09-09 19:17:17 +02:00
joachimschmidt557
481bd4761a
stage2 ARM: remove remaining uses of binOp{Register,Immediate} 2022-09-09 19:17:17 +02:00
joachimschmidt557
95b8a5f157
stage2 ARM: extract remaining operations out of binOp 2022-09-09 19:17:17 +02:00
joachimschmidt557
fdb2c80bdc
stage2 ARM: extract mul, div, and mod out of binOp 2022-09-09 19:17:17 +02:00
joachimschmidt557
ed4be06883
stage2 ARM: extract add+sub from binOp
This commit also lays the groundwork for further extractions from
binOp.
2022-09-09 19:17:17 +02:00
joachimschmidt557
86dd123392
stage2 ARM: move cmp to new allocReg mechanism; remove from binOp 2022-09-09 19:17:17 +02:00
joachimschmidt557
0414ef591a
stage2 ARM: introduce allocRegs
This new register allocation mechanism which is designed to be more
generic and flexible will replace binOp.
2022-09-09 19:17:16 +02:00
joachimschmidt557
28cc363947
stage2 ARM: improve Mir representation of mov and cmp 2022-09-09 19:17:13 +02:00
Jakub Konka
601f2147e0 coff: cleanup relocations; remove COFF support from other backends
Given that COFF will want to support PIC from ground-up, there is no
point in leaving outdated code for COFF in other backends such as
arm or aarch64. Instead, when we are ready to look into those, we
can start figuring out what to add and where.
2022-08-30 10:42:21 +02:00
Jakub Konka
90b3599c68 coff: reorganize the linker 2022-08-30 10:42:21 +02:00
Veikka Tuominen
40eac90280
Merge pull request #12416 from Vexu/stage2-safety
Stage2 error set safety improvements
2022-08-15 11:32:26 +03:00
joachimschmidt557
c9d9fd53a6
stage2 ARM: add inline memcpy to genSetStack 2022-08-13 17:00:03 +02:00
joachimschmidt557
91969ad908
stage2 ARM: Fix tracking of function return values 2022-08-13 17:00:03 +02:00
joachimschmidt557
4c5156544b
stage2 ARM: pass stack arguments in opposite order
Earlier arguments have a smaller address (i.e. towards the bottom of
the stack)
2022-08-13 17:00:00 +02:00
Veikka Tuominen
7c9979a02e stage2: generate a switch for @errSetCast safety 2022-08-12 11:40:37 +03:00
Veikka Tuominen
f46d7304b1 stage2: add runtime safety for invalid enum values 2022-08-05 22:13:58 +03:00
antlilja
cd8070f94f
Removed param_names from Fn inside Module.zig
Removed the copy of param_names inside of Fn and changed to
implementation of getParamName to fetch to parameter name from the ZIR.
The signature of getParamName was also changed to take an additional
*Module argument.
2022-08-01 14:51:50 +02:00
joachimschmidt557
0fc79d602b stage2 ARM: more support for switch statements 2022-07-28 20:44:32 +00:00
Veikka Tuominen
d75fa86d70 stage2: implement @setFloatMode 2022-07-23 15:40:12 +03:00
joachimschmidt557
f89ace4d04
stage2 ARM: add integer modulo with constant power-of-two rhs 2022-07-12 23:22:15 +02:00
joachimschmidt557
47d1874218
stage2 ARM: implement division by constant int power-of-two divisors 2022-07-12 22:43:55 +02:00
Andrew Kelley
6bc6e47b15 stage2: lower float negation explicitly
Rather than lowering float negation as `0.0 - x`.

 * Add AIR instruction for float negation.
 * Add compiler-rt functions for f128, f80 negation

closes #11853
2022-06-30 00:02:00 -07:00
joachimschmidt557
960c142060 stage2 ARM: implement basic intCast and error union wrapping 2022-06-25 21:16:51 +02:00
Veikka Tuominen
0333ff4476 stage2: make error{} the same size as anyerror
Having `error{}` be a zero bit type causes issues when it interracts
with empty inferred error sets which are the same size as `anyerror`.
2022-06-11 23:49:33 +03:00
Andrew Kelley
d1bfc83774
Merge pull request #11783 from ziglang/stage2-try
introduce a "try" ZIR and AIR instruction
2022-06-06 19:01:39 -04:00
Jakub Konka
e05de31a5f dwarf: fix incorrect type reloc for unions
Split type relocs into two kinds: local and global. Global relocs
use a global type resolver and calculate offset to the existing
definition of a type abbreviation.

Local relocs use offset in the abbrev section of the containing
atom plus addend to generate a local relocation.
2022-06-06 19:58:51 +02:00
joachimschmidt557
a34f3ff04a
stage2 ARM: implement try AIR instruction 2022-06-06 14:22:40 +02:00
Andrew Kelley
ef885a78d6 stage2: implement the new "try" ZIR/AIR instruction
Implements semantic analysis for the new try/try_inline ZIR
instruction. Adds the new try/try_ptr AIR instructions and implements
them for the LLVM backend.

Fixes not calling rvalue() for tryExpr in AstGen.

This is part of an effort to implement #11772.
2022-06-05 10:37:08 +02:00
joachimschmidt557
d5ee451177
stage2 ARM: introduce support for basic switch expressions 2022-06-04 19:58:34 +02:00
joachimschmidt557
4fdacca512
stage2 ARM: rework cmp in preparation for switch 2022-06-02 20:19:18 +02:00
Ali Chraghi
0e6285c8fc math: make cast return optional instead of an error 2022-05-27 16:43:33 -04:00
Andrew Kelley
c711c788f0 stage2: fixes for error unions, optionals, errors
* `?E` where E is an error set with only one field now lowers the same
   as `bool`.
 * Fix implementation of errUnionErrOffset and errUnionPayloadOffset to
   properly compute the offset of each field. Also name them the same
   as the corresponding LLVM functions and have the same function
   signature, to avoid confusion. This fixes a bug where wasm was
   passing the error union type instead of the payload type.
 * Fix C backend handling of optionals with zero-bit payload types.
 * C backend: separate out airOptionalPayload and airOptionalPayloadPtr
   which reduces branching and cleans up control flow.
 * Make Type.isNoReturn return true for error sets with no fields.
 * Make `?error{}` have only one possible value (null).
2022-05-24 15:34:52 -07:00
joachimschmidt557
c847a462ae stage2 ARM: update to new union layout 2022-05-24 15:34:52 -07:00
joachimschmidt557
b56b4428a3 stage2 ARM: fix recursive fibonacci
Some handling of register_c_flag/register_v_flag was incorrect.
2022-05-22 21:02:32 +02:00
joachimschmidt557
9747303d16 stage2 ARM: Introduce MCValue.cpsr_flags
MCValue.cpsr_flags replaces
MCValue.compare_flags_{signed,unsigned}. This simplifies a lot of
stuff and enables an MCValue to represent only the overflow bits in
the CPU (previously, it was only possible to represent a register +
the overflow bits).
2022-05-21 22:15:04 +02:00
Jakub Konka
e95dfac03e regalloc: make register class bitmask non-optional 2022-05-19 23:54:48 +02:00
Jakub Konka
549174f743 regalloc: allow for optional selector mask when allocating 2022-05-19 19:39:32 +02:00
Andrew Kelley
b6798c26ef stage2: fix pointer arithmetic result type
This makes it so the result of doing pointer arithmetic creates a new
pointer type that has adjusted alignment.
2022-05-17 23:50:38 -07:00
Veikka Tuominen
66c3988e5e stage2: disable error return tracing on unsupported targets 2022-05-16 17:42:51 -07:00
Veikka Tuominen
eee8fffec7 stage2: implement error return traces 2022-05-16 17:42:51 -07:00
Jakub Konka
7f96ca101a arm: sub_with_overflow should always track V flag 2022-05-16 13:55:26 -07:00