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stage2 ARM: introduce allocRegs
This new register allocation mechanism which is designed to be more generic and flexible will replace binOp.
This commit is contained in:
joachimschmidt557
parent
28cc363947
commit
0414ef591a
@ -2232,7 +2232,13 @@ fn airUnaryMath(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ un_op, .none, .none });
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}
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fn reuseOperand(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, op_index: Liveness.OperandInt, mcv: MCValue) bool {
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fn reuseOperand(
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self: *Self,
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inst: Air.Inst.Index,
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operand: Air.Inst.Ref,
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op_index: Liveness.OperandInt,
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mcv: MCValue,
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) bool {
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if (!self.liveness.operandDies(inst, op_index))
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return false;
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@ -2580,39 +2586,206 @@ fn airFieldParentPtr(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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/// Allocates a new register. If Inst in non-null, additionally tracks
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/// this register and the corresponding int and removes all previous
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/// tracking. Does not do the actual moving (that is handled by
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/// genSetReg).
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fn prepareNewRegForMoving(
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/// An argument to a Mir instruction which is read (and possibly also
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/// written to) by the respective instruction
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const ReadArg = struct {
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ty: Type,
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bind: Bind,
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class: RegisterManager.RegisterBitSet,
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reg: *Register,
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const Bind = union(enum) {
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inst: Air.Inst.Ref,
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mcv: MCValue,
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fn resolveToMcv(bind: Bind, function: *Self) InnerError!MCValue {
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return switch (bind) {
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.inst => |inst| try function.resolveInst(inst),
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.mcv => |mcv| mcv,
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};
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}
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};
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};
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/// An argument to a Mir instruction which is written to (but not read
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/// from) by the respective instruction
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const WriteArg = struct {
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ty: Type,
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bind: Bind,
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class: RegisterManager.RegisterBitSet,
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reg: *Register,
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const Bind = union(enum) {
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reg: Register,
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none: void,
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};
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};
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/// Holds all data necessary for enabling the potential reuse of
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/// operand registers as destinations
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const ReuseMetadata = struct {
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corresponding_inst: Air.Inst.Index,
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/// Maps every element index of read_args to the corresponding
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/// index in the Air instruction
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///
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/// When the order of read_args corresponds exactly to the order
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/// of the inputs of the Air instruction, this would be e.g.
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/// &.{ 0, 1 }. However, when the order is not the same or some
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/// inputs to the Air instruction are omitted (e.g. when they can
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/// be represented as immediates to the Mir instruction),
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/// operand_mapping should reflect that fact.
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operand_mapping: []const Liveness.OperandInt,
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};
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/// Allocate a set of registers for use as arguments for a Mir
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/// instruction
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///
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/// If the Mir instruction these registers are allocated for
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/// corresponds exactly to a single Air instruction, populate
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/// reuse_metadata in order to enable potential reuse of an operand as
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/// the destination (provided that that operand dies in this
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/// instruction).
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///
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/// Reusing an operand register as destination is the only time two
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/// arguments may share the same register. In all other cases,
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/// allocRegs guarantees that a register will never be allocated to
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/// more than one argument.
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///
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/// Furthermore, allocReg guarantees that all arguments which are
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/// already bound to registers before calling allocRegs will not
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/// change their register binding. This is done by locking these
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/// registers.
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fn allocRegs(
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self: *Self,
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track_inst: ?Air.Inst.Index,
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register_class: RegisterManager.RegisterBitSet,
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mcv: MCValue,
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) !Register {
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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const reg = try self.register_manager.allocReg(track_inst, register_class);
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read_args: []const ReadArg,
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write_args: []const WriteArg,
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reuse_metadata: ?ReuseMetadata,
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) InnerError!void {
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// Air instructions have either one output or none (cmp)
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assert(!(reuse_metadata != null and write_args.len > 1)); // see note above
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if (track_inst) |inst| {
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// Overwrite the MCValue associated with this inst
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branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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// The operand mapping is a 1:1 mapping of read args to their
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// corresponding operand index in the Air instruction
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assert(!(reuse_metadata != null and reuse_metadata.?.operand_mapping.len != read_args.len)); // see note above
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// If the previous MCValue occupied some space we track, we
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// need to make sure it is marked as free now.
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switch (mcv) {
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.cpsr_flags => {
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assert(self.cpsr_flags_inst.? == inst);
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self.cpsr_flags_inst = null;
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},
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.register => |prev_reg| {
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assert(!self.register_manager.isRegFree(prev_reg));
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self.register_manager.freeReg(prev_reg);
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},
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else => {},
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const locks = try self.gpa.alloc(?RegisterLock, read_args.len + write_args.len);
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defer self.gpa.free(locks);
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const read_locks = locks[0..read_args.len];
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const write_locks = locks[read_args.len..];
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std.mem.set(?RegisterLock, locks, null);
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defer for (locks) |lock| {
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if (lock) |locked_reg| self.register_manager.unlockReg(locked_reg);
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};
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// When we reuse a read_arg as a destination, the corresponding
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// MCValue of the read_arg will be set to .dead. In that case, we
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// skip allocating this read_arg.
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var reused_read_arg: ?usize = null;
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// Lock all args which are already allocated to registers
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for (read_args) |arg, i| {
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const mcv = try arg.bind.resolveToMcv(self);
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if (mcv == .register) {
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read_locks[i] = self.register_manager.lockReg(mcv.register);
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}
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}
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return reg;
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for (write_args) |arg, i| {
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if (arg.bind == .reg) {
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write_locks[i] = self.register_manager.lockReg(arg.bind.reg);
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}
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}
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// Allocate registers for all args which aren't allocated to
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// registers yet
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for (read_args) |arg, i| {
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const mcv = try arg.bind.resolveToMcv(self);
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if (mcv == .register) {
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arg.reg.* = mcv.register;
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} else {
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const track_inst: ?Air.Inst.Index = switch (arg.bind) {
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.inst => |inst| Air.refToIndex(inst).?,
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else => null,
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};
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arg.reg.* = try self.register_manager.allocReg(track_inst, arg.class);
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read_locks[i] = self.register_manager.lockReg(arg.reg.*);
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}
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}
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if (reuse_metadata != null and write_args.len > 0) {
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const inst = reuse_metadata.?.corresponding_inst;
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const operand_mapping = reuse_metadata.?.operand_mapping;
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const arg = write_args[0];
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if (arg.bind == .reg) {
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arg.reg.* = arg.bind.reg;
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} else {
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reuse_operand: for (read_args) |read_arg, i| {
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if (read_arg.bind == .inst) {
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const operand = read_arg.bind.inst;
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const mcv = try self.resolveInst(operand);
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if (mcv == .register and
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std.meta.eql(arg.class, read_arg.class) and
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self.reuseOperand(inst, operand, operand_mapping[i], mcv))
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{
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arg.reg.* = mcv.register;
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write_locks[0] = null;
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reused_read_arg = i;
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break :reuse_operand;
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}
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}
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} else {
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arg.reg.* = try self.register_manager.allocReg(inst, arg.class);
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write_locks[0] = self.register_manager.lockReg(arg.reg.*);
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}
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}
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} else {
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for (write_args) |arg, i| {
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if (arg.bind == .reg) {
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arg.reg.* = arg.bind.reg;
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} else {
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arg.reg.* = try self.register_manager.allocReg(null, arg.class);
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write_locks[i] = self.register_manager.lockReg(arg.reg.*);
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}
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}
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}
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// For all read_args which need to be moved from non-register to
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// register, perform the move
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for (read_args) |arg, i| {
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if (reused_read_arg) |j| {
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// Check whether this read_arg was reused
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if (i == j) continue;
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}
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const mcv = try arg.bind.resolveToMcv(self);
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if (mcv != .register) {
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if (arg.bind == .inst) {
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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const inst = Air.refToIndex(arg.bind.inst).?;
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// Overwrite the MCValue associated with this inst
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branch.inst_table.putAssumeCapacity(inst, .{ .register = arg.reg.* });
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// If the previous MCValue occupied some space we track, we
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// need to make sure it is marked as free now.
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switch (mcv) {
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.cpsr_flags => {
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assert(self.cpsr_flags_inst.? == inst);
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self.cpsr_flags_inst = null;
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},
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.register => |prev_reg| {
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assert(!self.register_manager.isRegFree(prev_reg));
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self.register_manager.freeReg(prev_reg);
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},
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else => {},
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}
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}
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try self.genSetReg(arg.ty, arg.reg.*, mcv);
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}
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}
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}
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/// Don't call this function directly. Use binOp instead.
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@ -2632,50 +2805,33 @@ fn binOpRegister(
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rhs_ty: Type,
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metadata: ?BinOpMetadata,
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) !MCValue {
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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var lhs_reg: Register = undefined;
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var rhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const lhs_lock: ?RegisterLock = if (lhs_is_register)
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self.register_manager.lockReg(lhs.register)
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const lhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.lhs }
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else
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null;
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defer if (lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (metadata) |md| inst: {
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break :inst Air.refToIndex(md.lhs).?;
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} else null;
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break :blk try self.prepareNewRegForMoving(track_inst, gp, lhs);
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ReadArg.Bind{ .mcv = lhs };
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const rhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.rhs }
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else
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ReadArg.Bind{ .mcv = rhs };
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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.{ .ty = rhs_ty, .bind = rhs_bind, .class = gp, .reg = &rhs_reg },
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};
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const new_lhs_lock = self.register_manager.lockReg(lhs_reg);
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const rhs_reg = if (rhs_is_register) rhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (metadata) |md| inst: {
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break :inst Air.refToIndex(md.rhs).?;
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} else null;
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break :blk try self.prepareNewRegForMoving(track_inst, gp, rhs);
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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const new_rhs_lock = self.register_manager.lockReg(rhs_reg);
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defer if (new_rhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_reg = switch (mir_tag) {
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.cmp => undefined, // cmp has no destination regardless
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else => if (metadata) |md| blk: {
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if (lhs_is_register and self.reuseOperand(md.inst, md.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else if (rhs_is_register and self.reuseOperand(md.inst, md.rhs, 1, rhs)) {
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break :blk rhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(md.inst, gp);
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}
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} else try self.register_manager.allocReg(null, gp),
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};
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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try self.allocRegs(
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&read_args,
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if (mir_tag == .cmp) &.{} else &write_args,
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if (metadata) |md| .{
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.corresponding_inst = md.inst,
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.operand_mapping = &.{ 0, 1 },
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} else null,
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);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add,
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@ -2741,43 +2897,33 @@ fn binOpImmediate(
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lhs_and_rhs_swapped: bool,
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metadata: ?BinOpMetadata,
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) !MCValue {
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const lhs_is_register = lhs == .register;
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var lhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const lhs_lock: ?RegisterLock = if (lhs_is_register)
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self.register_manager.lockReg(lhs.register)
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else
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null;
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defer if (lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (metadata) |md| inst: {
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break :inst Air.refToIndex(
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if (lhs_and_rhs_swapped) md.rhs else md.lhs,
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).?;
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} else null;
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break :blk try self.prepareNewRegForMoving(track_inst, gp, lhs);
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};
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const new_lhs_lock = self.register_manager.lockReg(lhs_reg);
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_reg = switch (mir_tag) {
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.cmp => undefined, // cmp has no destination reg
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else => if (metadata) |md| blk: {
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if (lhs_is_register and self.reuseOperand(
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md.inst,
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if (lhs_and_rhs_swapped) md.rhs else md.lhs,
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if (lhs_and_rhs_swapped) 1 else 0,
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lhs,
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)) {
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break :blk lhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(md.inst, gp);
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}
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} else try self.register_manager.allocReg(null, gp),
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const lhs_bind = blk: {
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if (metadata) |md| {
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const inst = if (lhs_and_rhs_swapped) md.rhs else md.lhs;
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break :blk ReadArg.Bind{ .inst = inst };
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} else {
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break :blk ReadArg.Bind{ .mcv = lhs };
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}
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};
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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};
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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const operand_mapping: []const Liveness.OperandInt = if (lhs_and_rhs_swapped) &.{1} else &.{0};
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try self.allocRegs(
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&read_args,
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if (mir_tag == .cmp) &.{} else &write_args,
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if (metadata) |md| .{
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.corresponding_inst = md.inst,
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.operand_mapping = operand_mapping,
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} else null,
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);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add,
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@ -2983,33 +3129,27 @@ fn binOp(
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if (std.math.isPowerOfTwo(imm)) {
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const log2 = std.math.log2_int(u32, imm);
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const lhs_is_register = lhs == .register;
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var lhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const lhs_lock: ?RegisterLock = if (lhs_is_register)
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self.register_manager.lockReg(lhs.register)
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const lhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.lhs }
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else
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null;
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defer if (lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (metadata) |md| inst: {
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break :inst Air.refToIndex(md.lhs).?;
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} else null;
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break :blk try self.prepareNewRegForMoving(track_inst, gp, lhs);
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ReadArg.Bind{ .mcv = lhs };
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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};
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const new_lhs_lock = self.register_manager.lockReg(lhs_reg);
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_reg = if (metadata) |md| blk: {
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if (lhs_is_register and self.reuseOperand(md.inst, md.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(md.inst, gp);
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||||
}
|
||||
} else try self.register_manager.allocReg(null, gp);
|
||||
|
||||
if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
|
||||
const write_args = [_]WriteArg{
|
||||
.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
|
||||
};
|
||||
try self.allocRegs(
|
||||
&read_args,
|
||||
&write_args,
|
||||
if (metadata) |md| .{
|
||||
.corresponding_inst = md.inst,
|
||||
.operand_mapping = &.{0},
|
||||
} else null,
|
||||
);
|
||||
|
||||
try self.truncRegister(lhs_reg, dest_reg, int_info.signedness, log2);
|
||||
return MCValue{ .register = dest_reg };
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user