mirror of
https://github.com/ziglang/zig.git
synced 2026-02-12 20:37:54 +00:00
stage2 ARM: improve Mir representation of mov and cmp
This commit is contained in:
joachimschmidt557
parent
9e070b653c
commit
28cc363947
@ -438,9 +438,8 @@ fn gen(self: *Self) !void {
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// mov fp, sp
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = .fp,
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.rn = .r0,
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.op = Instruction.Operand.reg(.sp, Instruction.Operand.Shift.none),
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} },
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});
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@ -531,9 +530,8 @@ fn gen(self: *Self) !void {
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// mov sp, fp
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = .sp,
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.rn = .r0,
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.op = Instruction.Operand.reg(.fp, Instruction.Operand.Shift.none),
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} },
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});
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@ -1240,9 +1238,8 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
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_ = try self.addInst(.{
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.tag = .mvn,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = dest_reg,
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.rn = undefined,
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.op = Instruction.Operand.reg(op_reg, Instruction.Operand.Shift.none),
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} },
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});
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@ -1337,9 +1334,8 @@ fn minMax(
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_ = try self.addInst(.{
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.tag = .mov,
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.cond = cond_choose_lhs,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = dest_reg,
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.rn = .r0,
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.op = Instruction.Operand.reg(lhs_reg, Instruction.Operand.Shift.none),
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} },
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});
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@ -1348,9 +1344,8 @@ fn minMax(
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_ = try self.addInst(.{
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.tag = .mov,
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.cond = cond_choose_rhs,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = dest_reg,
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.rn = .r0,
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.op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
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} },
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});
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@ -1682,9 +1677,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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// mov rdlo, #0
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = rdlo,
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.rn = .r0,
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.op = Instruction.Operand.fromU32(0).?,
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} },
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});
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@ -1693,9 +1687,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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_ = try self.addInst(.{
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.tag = .mov,
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.cond = .ne,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = rdlo,
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.rn = .r0,
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.op = Instruction.Operand.fromU32(1).?,
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} },
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});
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@ -1707,9 +1700,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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_ = try self.addInst(.{
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.tag = .mov,
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.cond = .ne,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = rdlo,
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.rn = .r0,
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.op = Instruction.Operand.fromU32(1).?,
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} },
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});
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@ -2670,7 +2662,7 @@ fn binOpRegister(
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defer if (new_rhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_reg = switch (mir_tag) {
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.cmp => .r0, // cmp has no destination regardless
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.cmp => undefined, // cmp has no destination regardless
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else => if (metadata) |md| blk: {
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if (lhs_is_register and self.reuseOperand(md.inst, md.lhs, 0, lhs)) {
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break :blk lhs_reg;
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@ -2690,7 +2682,6 @@ fn binOpRegister(
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.adds,
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.sub,
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.subs,
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.cmp,
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.@"and",
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.orr,
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.eor,
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@ -2699,6 +2690,10 @@ fn binOpRegister(
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.rn = lhs_reg,
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.op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
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} },
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.cmp => .{ .r_op_cmp = .{
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.rn = lhs_reg,
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.op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
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} },
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.lsl,
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.asr,
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.lsr,
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@ -2767,7 +2762,7 @@ fn binOpImmediate(
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_reg = switch (mir_tag) {
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.cmp => .r0, // cmp has no destination reg
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.cmp => undefined, // cmp has no destination reg
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else => if (metadata) |md| blk: {
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if (lhs_is_register and self.reuseOperand(
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md.inst,
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@ -2789,7 +2784,6 @@ fn binOpImmediate(
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.adds,
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.sub,
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.subs,
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.cmp,
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.@"and",
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.orr,
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.eor,
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@ -2798,6 +2792,10 @@ fn binOpImmediate(
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.rn = lhs_reg,
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.op = Instruction.Operand.fromU32(rhs.immediate).?,
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} },
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.cmp => .{ .r_op_cmp = .{
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.rn = lhs_reg,
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.op = Instruction.Operand.fromU32(rhs.immediate).?,
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} },
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.lsl,
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.asr,
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.lsr,
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@ -3312,9 +3310,8 @@ fn genInlineMemcpy(
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// mov count, #0
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = count,
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.rn = .r0,
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.op = Instruction.Operand.imm(0, 0),
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} },
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});
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@ -3323,8 +3320,7 @@ fn genInlineMemcpy(
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// cmp count, len
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_ = try self.addInst(.{
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.tag = .cmp,
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.data = .{ .rr_op = .{
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.rd = .r0,
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.data = .{ .r_op_cmp = .{
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.rn = count,
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.op = Instruction.Operand.reg(len, Instruction.Operand.Shift.none),
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} },
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@ -3418,9 +3414,8 @@ fn genInlineMemsetCode(
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// mov count, #0
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = count,
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.rn = .r0,
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.op = Instruction.Operand.imm(0, 0),
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} },
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});
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@ -3429,8 +3424,7 @@ fn genInlineMemsetCode(
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// cmp count, len
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_ = try self.addInst(.{
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.tag = .cmp,
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.data = .{ .rr_op = .{
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.rd = .r0,
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.data = .{ .r_op_cmp = .{
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.rn = count,
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.op = Instruction.Operand.reg(len, Instruction.Operand.Shift.none),
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} },
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@ -4020,9 +4014,7 @@ fn condBr(self: *Self, condition: MCValue) !Mir.Inst.Index {
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// bne ...
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_ = try self.addInst(.{
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.tag = .cmp,
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.cond = .al,
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.data = .{ .rr_op = .{
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.rd = .r0,
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.data = .{ .r_op_cmp = .{
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.rn = reg,
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.op = Instruction.Operand.imm(1, 0),
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} },
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@ -4196,8 +4188,7 @@ fn isNull(self: *Self, ty: Type, operand: MCValue) !MCValue {
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_ = try self.addInst(.{
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.tag = .cmp,
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.data = .{ .rr_op = .{
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.rd = undefined,
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.data = .{ .r_op_cmp = .{
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.rn = reg_mcv.register,
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.op = Instruction.Operand.fromU32(0).?,
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} },
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@ -4832,9 +4823,8 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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.register_v_flag => .vs,
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else => unreachable,
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},
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = cond_reg,
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.rn = .r0,
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.op = Instruction.Operand.fromU32(1).?,
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} },
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});
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@ -4935,9 +4925,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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// mov reg, 0
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = reg,
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.rn = .r0,
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.op = zero,
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} },
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});
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@ -4946,9 +4935,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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_ = try self.addInst(.{
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.tag = .mov,
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.cond = condition,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = reg,
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.rn = .r0,
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.op = one,
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} },
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});
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@ -4957,18 +4945,16 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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if (Instruction.Operand.fromU32(x)) |op| {
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = reg,
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.rn = .r0,
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.op = op,
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} },
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});
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} else if (Instruction.Operand.fromU32(~x)) |op| {
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_ = try self.addInst(.{
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.tag = .mvn,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = reg,
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.rn = .r0,
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.op = op,
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} },
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});
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@ -4984,9 +4970,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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} else {
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = reg,
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.rn = .r0,
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.op = Instruction.Operand.imm(@truncate(u8, x), 0),
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} },
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});
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@ -5028,9 +5013,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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// orr reg, reg, #0xdd, 8
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = reg,
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.rn = .r0,
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.op = Instruction.Operand.imm(@truncate(u8, x), 0),
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} },
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});
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@ -5069,9 +5053,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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// mov reg, src_reg
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.data = .{ .r_op_mov = .{
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.rd = reg,
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.rn = .r0,
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.op = Instruction.Operand.reg(src_reg, Instruction.Operand.Shift.none),
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} },
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});
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@ -385,20 +385,44 @@ fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
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fn mirDataProcessing(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const cond = emit.mir.instructions.items(.cond)[inst];
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const rr_op = emit.mir.instructions.items(.data)[inst].rr_op;
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switch (tag) {
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.add => try emit.writeInstruction(Instruction.add(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.adds => try emit.writeInstruction(Instruction.adds(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.@"and" => try emit.writeInstruction(Instruction.@"and"(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.cmp => try emit.writeInstruction(Instruction.cmp(cond, rr_op.rn, rr_op.op)),
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.eor => try emit.writeInstruction(Instruction.eor(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.mov => try emit.writeInstruction(Instruction.mov(cond, rr_op.rd, rr_op.op)),
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.mvn => try emit.writeInstruction(Instruction.mvn(cond, rr_op.rd, rr_op.op)),
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.orr => try emit.writeInstruction(Instruction.orr(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.rsb => try emit.writeInstruction(Instruction.rsb(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.sub => try emit.writeInstruction(Instruction.sub(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.subs => try emit.writeInstruction(Instruction.subs(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.add,
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.adds,
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.@"and",
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.eor,
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.orr,
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.rsb,
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.sub,
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.subs,
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=> {
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const rr_op = emit.mir.instructions.items(.data)[inst].rr_op;
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switch (tag) {
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.add => try emit.writeInstruction(Instruction.add(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.adds => try emit.writeInstruction(Instruction.adds(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.@"and" => try emit.writeInstruction(Instruction.@"and"(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.eor => try emit.writeInstruction(Instruction.eor(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.orr => try emit.writeInstruction(Instruction.orr(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.rsb => try emit.writeInstruction(Instruction.rsb(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.sub => try emit.writeInstruction(Instruction.sub(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.subs => try emit.writeInstruction(Instruction.subs(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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else => unreachable,
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}
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},
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.cmp => {
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const r_op_cmp = emit.mir.instructions.items(.data)[inst].r_op_cmp;
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try emit.writeInstruction(Instruction.cmp(cond, r_op_cmp.rn, r_op_cmp.op));
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},
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.mov,
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.mvn,
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=> {
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const r_op_mov = emit.mir.instructions.items(.data)[inst].r_op_mov;
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switch (tag) {
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.mov => try emit.writeInstruction(Instruction.mov(cond, r_op_mov.rd, r_op_mov.op)),
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.mvn => try emit.writeInstruction(Instruction.mvn(cond, r_op_mov.rd, r_op_mov.op)),
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else => unreachable,
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}
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},
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else => unreachable,
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}
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}
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@ -166,6 +166,20 @@ pub const Inst = struct {
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rd: Register,
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imm16: u16,
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},
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/// A register and an operand
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///
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/// Used by mov and mvn
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r_op_mov: struct {
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rd: Register,
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op: bits.Instruction.Operand,
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},
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/// A register and an operand
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///
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/// Used by cmp
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r_op_cmp: struct {
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rn: Register,
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op: bits.Instruction.Operand,
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},
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/// Two registers and a shift amount
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///
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/// Used by e.g. lsl
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