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stage2 ARM: extract add+sub from binOp
This commit also lays the groundwork for further extractions from binOp.
This commit is contained in:
joachimschmidt557
parent
86dd123392
commit
ed4be06883
@ -1401,19 +1401,26 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {
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fn airBinOp(self: *Self, inst: Air.Inst.Index, tag: Air.Inst.Tag) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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const rhs_ty = self.air.typeOf(bin_op.rhs);
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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try self.binOp(tag, lhs, rhs, lhs_ty, rhs_ty, BinOpMetadata{
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.lhs = bin_op.lhs,
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.rhs = bin_op.rhs,
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.inst = inst,
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});
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const lhs_bind: ReadArg.Bind = .{ .inst = bin_op.lhs };
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const rhs_bind: ReadArg.Bind = .{ .inst = bin_op.rhs };
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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switch (tag) {
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.add,
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.sub,
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=> break :result try self.addSub(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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else => break :result try self.binOp(tag, lhs, rhs, lhs_ty, rhs_ty, BinOpMetadata{
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.lhs = bin_op.lhs,
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.rhs = bin_op.rhs,
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.inst = inst,
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}),
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}
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -1459,8 +1466,8 @@ fn airOverflow(self: *Self, inst: Air.Inst.Index) !void {
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const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
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const extra = self.air.extraData(Air.Bin, ty_pl.payload).data;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const lhs = try self.resolveInst(extra.lhs);
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const rhs = try self.resolveInst(extra.rhs);
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const lhs_bind: ReadArg.Bind = .{ .inst = extra.lhs };
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const rhs_bind: ReadArg.Bind = .{ .inst = extra.rhs };
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const lhs_ty = self.air.typeOf(extra.lhs);
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const rhs_ty = self.air.typeOf(extra.rhs);
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@ -1485,7 +1492,7 @@ fn airOverflow(self: *Self, inst: Air.Inst.Index) !void {
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.sub_with_overflow => .sub,
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else => unreachable,
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};
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const dest = try self.binOp(base_tag, lhs, rhs, lhs_ty, rhs_ty, null);
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const dest = try self.addSub(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, null);
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const dest_reg = dest.register;
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const dest_reg_lock = self.register_manager.lockRegAssumeUnused(dest_reg);
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defer self.register_manager.unlockReg(dest_reg_lock);
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@ -1511,6 +1518,9 @@ fn airOverflow(self: *Self, inst: Air.Inst.Index) !void {
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break :result MCValue{ .stack_offset = stack_offset };
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} else if (int_info.bits == 32) {
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const lhs = try self.resolveInst(extra.lhs);
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const rhs = try self.resolveInst(extra.rhs);
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// Only say yes if the operation is
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// commutative, i.e. we can swap both of the
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// operands
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@ -2600,26 +2610,10 @@ fn structFieldPtr(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, inde
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break :result MCValue{ .ptr_stack_offset = off - struct_field_offset };
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},
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else => {
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const offset_reg = try self.copyToTmpRegister(ptr_ty, .{
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.immediate = struct_field_offset,
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});
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const offset_reg_lock = self.register_manager.lockRegAssumeUnused(offset_reg);
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defer self.register_manager.unlockReg(offset_reg_lock);
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const lhs_bind: ReadArg.Bind = .{ .mcv = mcv };
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const rhs_bind: ReadArg.Bind = .{ .mcv = .{ .immediate = struct_field_offset } };
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const addr_reg = try self.copyToTmpRegister(ptr_ty, mcv);
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const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
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defer self.register_manager.unlockReg(addr_reg_lock);
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const dest = try self.binOp(
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.add,
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.{ .register = addr_reg },
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.{ .register = offset_reg },
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Type.usize,
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Type.usize,
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null,
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);
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break :result dest;
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break :result try self.addSub(.add, lhs_bind, rhs_bind, Type.usize, Type.usize, null);
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},
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}
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};
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@ -2708,6 +2702,25 @@ const ReadArg = struct {
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.mcv => |mcv| mcv,
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};
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}
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fn resolveToImmediate(bind: Bind, function: *Self) InnerError!?u32 {
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switch (bind) {
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.inst => |inst| {
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// TODO resolve independently of inst_table
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const mcv = try function.resolveInst(inst);
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switch (mcv) {
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.immediate => |imm| return imm,
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else => return null,
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}
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},
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.mcv => |mcv| {
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switch (mcv) {
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.immediate => |imm| return imm,
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else => return null,
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}
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},
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}
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}
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};
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};
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@ -3057,6 +3070,136 @@ fn binOpImmediate(
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return MCValue{ .register = dest_reg };
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}
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/// TODO
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fn binOpRegisterNew(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) !MCValue {
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var lhs_reg: Register = undefined;
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var rhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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.{ .ty = rhs_ty, .bind = rhs_bind, .class = gp, .reg = &rhs_reg },
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};
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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try self.allocRegs(
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&read_args,
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&write_args,
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if (maybe_inst) |inst| .{
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.corresponding_inst = inst,
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.operand_mapping = &.{ 0, 1 },
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} else null,
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);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add,
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.adds,
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.sub,
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.subs,
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.@"and",
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.orr,
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.eor,
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=> .{ .rr_op = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
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} },
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.lsl,
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.asr,
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.lsr,
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=> .{ .rr_shift = .{
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.rd = dest_reg,
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.rm = lhs_reg,
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.shift_amount = Instruction.ShiftAmount.reg(rhs_reg),
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} },
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.mul,
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.smulbb,
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=> .{ .rrr = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.rm = rhs_reg,
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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/// TODO
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fn binOpImmediateNew(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_immediate: u32,
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lhs_ty: Type,
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lhs_and_rhs_swapped: bool,
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maybe_inst: ?Air.Inst.Index,
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) !MCValue {
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var lhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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};
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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const operand_mapping: []const Liveness.OperandInt = if (lhs_and_rhs_swapped) &.{1} else &.{0};
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try self.allocRegs(
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&read_args,
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&write_args,
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if (maybe_inst) |inst| .{
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.corresponding_inst = inst,
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.operand_mapping = operand_mapping,
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} else null,
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);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add,
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.adds,
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.sub,
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.subs,
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.@"and",
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.orr,
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.eor,
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=> .{ .rr_op = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.op = Instruction.Operand.fromU32(rhs_immediate).?,
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} },
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.lsl,
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.asr,
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.lsr,
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=> .{ .rr_shift = .{
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.rd = dest_reg,
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.rm = lhs_reg,
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.shift_amount = Instruction.ShiftAmount.imm(@intCast(u5, rhs_immediate)),
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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const BinOpMetadata = struct {
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inst: Air.Inst.Index,
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lhs: Air.Inst.Ref,
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@ -3085,53 +3228,6 @@ fn binOp(
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metadata: ?BinOpMetadata,
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) InnerError!MCValue {
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switch (tag) {
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.add,
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.sub,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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// Only say yes if the operation is
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// commutative, i.e. we can swap both of the
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// operands
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const lhs_immediate_ok = switch (tag) {
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.add => lhs == .immediate and Instruction.Operand.fromU32(lhs.immediate) != null,
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.sub => false,
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else => unreachable,
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};
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const rhs_immediate_ok = switch (tag) {
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.add,
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.sub,
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=> rhs == .immediate and Instruction.Operand.fromU32(rhs.immediate) != null,
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else => unreachable,
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};
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add,
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.sub => .sub,
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(mir_tag, lhs, rhs, lhs_ty, false, metadata);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediate(mir_tag, rhs, lhs, rhs_ty, true, metadata);
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} else {
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return try self.binOpRegister(mir_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.mul => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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@ -3278,8 +3374,18 @@ fn binOp(
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else => unreachable,
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};
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const lhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.lhs }
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else
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ReadArg.Bind{ .mcv = lhs };
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const rhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.rhs }
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else
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ReadArg.Bind{ .mcv = rhs };
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// Generate an add/sub/mul
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const result = try self.binOp(base_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
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const maybe_inst: ?Air.Inst.Index = if (metadata) |md| md.inst else null;
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const result = try self.addSub(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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// Truncate if necessary
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switch (lhs_ty.zigTypeTag()) {
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@ -3463,6 +3569,63 @@ fn binOp(
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}
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}
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fn addSub(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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const lhs_immediate = try lhs_bind.resolveToImmediate(self);
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const rhs_immediate = try rhs_bind.resolveToImmediate(self);
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// Only say yes if the operation is
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// commutative, i.e. we can swap both of the
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// operands
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const lhs_immediate_ok = switch (tag) {
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.add => if (lhs_immediate) |imm| Instruction.Operand.fromU32(imm) != null else false,
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.sub => false,
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else => unreachable,
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};
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const rhs_immediate_ok = switch (tag) {
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.add,
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.sub,
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=> if (rhs_immediate) |imm| Instruction.Operand.fromU32(imm) != null else false,
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else => unreachable,
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};
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add,
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.sub => .sub,
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediateNew(mir_tag, lhs_bind, rhs_immediate.?, lhs_ty, false, maybe_inst);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediateNew(mir_tag, rhs_bind, lhs_immediate.?, rhs_ty, true, maybe_inst);
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} else {
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return try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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}
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fn genLdrRegister(self: *Self, dest_reg: Register, addr_reg: Register, ty: Type) !void {
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const abi_size = ty.abiSize(self.target.*);
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@ -4138,8 +4301,8 @@ fn cmp(
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var lhs_reg: Register = undefined;
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var rhs_reg: Register = undefined;
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const rhs_mcv = try rhs.resolveToMcv(self);
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const rhs_immediate_ok = rhs_mcv == .immediate and Instruction.Operand.fromU32(rhs_mcv.immediate) != null;
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const rhs_immediate = try rhs.resolveToImmediate(self);
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const rhs_immediate_ok = if (rhs_immediate) |imm| Instruction.Operand.fromU32(imm) != null else false;
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if (rhs_immediate_ok) {
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const read_args = [_]ReadArg{
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@ -4155,7 +4318,7 @@ fn cmp(
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.tag = .cmp,
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.data = .{ .r_op_cmp = .{
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.rn = lhs_reg,
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.op = Instruction.Operand.fromU32(rhs_mcv.immediate).?,
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.op = Instruction.Operand.fromU32(rhs_immediate.?).?,
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} },
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});
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} else {
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