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stage2 ARM: remove remaining uses of binOp{Register,Immediate}
This commit is contained in:
joachimschmidt557
parent
95b8a5f157
commit
481bd4761a
@ -1264,11 +1264,11 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
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fn minMax(
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self: *Self,
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tag: Air.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) !MCValue {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM min/max on floats", .{}),
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@ -1278,34 +1278,25 @@ fn minMax(
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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var lhs_reg: Register = undefined;
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var rhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const lhs_reg = switch (lhs) {
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.register => |r| r,
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else => try self.copyToTmpRegister(lhs_ty, lhs),
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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.{ .ty = rhs_ty, .bind = rhs_bind, .class = gp, .reg = &rhs_reg },
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};
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const lhs_reg_lock = self.register_manager.lockReg(lhs_reg);
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defer if (lhs_reg_lock) |reg| self.register_manager.unlockReg(reg);
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const rhs_reg = switch (rhs) {
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.register => |r| r,
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else => try self.copyToTmpRegister(rhs_ty, rhs),
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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const rhs_reg_lock = self.register_manager.lockReg(rhs_reg);
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defer if (rhs_reg_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_reg = if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (lhs_is_register and self.reuseOperand(inst, bin_op.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else if (rhs_is_register and self.reuseOperand(inst, bin_op.rhs, 1, rhs)) {
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break :blk rhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst, gp);
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}
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} else try self.register_manager.allocReg(null, gp);
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try self.allocRegs(
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&read_args,
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&write_args,
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if (maybe_inst) |inst| .{
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.corresponding_inst = inst,
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.operand_mapping = &.{ 0, 1 },
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} else null,
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);
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// lhs == reg should have been checked by airMinMax
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//
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@ -1369,15 +1360,17 @@ fn minMax(
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fn airMinMax(self: *Self, inst: Air.Inst.Index) !void {
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const tag = self.air.instructions.items(.tag)[inst];
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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const rhs_ty = self.air.typeOf(bin_op.rhs);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const lhs_bind: ReadArg.Bind = .{ .inst = bin_op.lhs };
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const rhs_bind: ReadArg.Bind = .{ .inst = bin_op.rhs };
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const lhs = try self.resolveInst(bin_op.lhs);
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if (bin_op.lhs == bin_op.rhs) break :result lhs;
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break :result try self.minMax(tag, inst, lhs, rhs, lhs_ty, rhs_ty);
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break :result try self.minMax(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst);
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -1538,21 +1531,21 @@ fn airOverflow(self: *Self, inst: Air.Inst.Index) !void {
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break :result MCValue{ .stack_offset = stack_offset };
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} else if (int_info.bits == 32) {
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const lhs = try self.resolveInst(extra.lhs);
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const rhs = try self.resolveInst(extra.rhs);
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const lhs_immediate = try lhs_bind.resolveToImmediate(self);
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const rhs_immediate = try rhs_bind.resolveToImmediate(self);
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// Only say yes if the operation is
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// commutative, i.e. we can swap both of the
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// operands
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const lhs_immediate_ok = switch (tag) {
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.add_with_overflow => lhs == .immediate and Instruction.Operand.fromU32(lhs.immediate) != null,
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.add_with_overflow => if (lhs_immediate) |imm| Instruction.Operand.fromU32(imm) != null else false,
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.sub_with_overflow => false,
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else => unreachable,
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};
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const rhs_immediate_ok = switch (tag) {
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.add_with_overflow,
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.sub_with_overflow,
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=> rhs == .immediate and Instruction.Operand.fromU32(rhs.immediate) != null,
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=> if (rhs_immediate) |imm| Instruction.Operand.fromU32(imm) != null else false,
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else => unreachable,
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};
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@ -1567,12 +1560,12 @@ fn airOverflow(self: *Self, inst: Air.Inst.Index) !void {
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const dest = blk: {
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if (rhs_immediate_ok) {
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break :blk try self.binOpImmediate(mir_tag, lhs, rhs, lhs_ty, false, null);
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break :blk try self.binOpImmediateNew(mir_tag, lhs_bind, rhs_immediate.?, lhs_ty, false, null);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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break :blk try self.binOpImmediate(mir_tag, rhs, lhs, rhs_ty, true, null);
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break :blk try self.binOpImmediateNew(mir_tag, rhs_bind, lhs_immediate.?, rhs_ty, true, null);
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} else {
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break :blk try self.binOpRegister(mir_tag, lhs, rhs, lhs_ty, rhs_ty, null);
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break :blk try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, null);
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}
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};
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@ -1599,8 +1592,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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const extra = self.air.extraData(Air.Bin, ty_pl.payload).data;
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if (self.liveness.isUnused(inst)) return self.finishAir(inst, .dead, .{ extra.lhs, extra.rhs, .none });
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const result: MCValue = result: {
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const lhs = try self.resolveInst(extra.lhs);
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const rhs = try self.resolveInst(extra.rhs);
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const lhs_bind: ReadArg.Bind = .{ .inst = extra.lhs };
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const rhs_bind: ReadArg.Bind = .{ .inst = extra.rhs };
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const lhs_ty = self.air.typeOf(extra.lhs);
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const rhs_ty = self.air.typeOf(extra.rhs);
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@ -1625,7 +1618,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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.unsigned => .mul,
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};
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const dest = try self.binOpRegister(base_tag, lhs, rhs, lhs_ty, rhs_ty, null);
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const dest = try self.binOpRegisterNew(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, null);
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const dest_reg = dest.register;
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const dest_reg_lock = self.register_manager.lockRegAssumeUnused(dest_reg);
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defer self.register_manager.unlockReg(dest_reg_lock);
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@ -1660,45 +1653,26 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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.unsigned => .umull,
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};
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// TODO extract umull etc. to binOpTwoRegister
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// once MCValue.rr is implemented
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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var lhs_reg: Register = undefined;
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var rhs_reg: Register = undefined;
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var rdhi: Register = undefined;
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var rdlo: Register = undefined;
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var truncated_reg: Register = undefined;
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const lhs_lock: ?RegisterLock = if (lhs_is_register)
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self.register_manager.lockReg(lhs.register)
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else
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null;
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defer if (lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const lhs_reg = if (lhs_is_register)
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lhs.register
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else
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try self.register_manager.allocReg(null, gp);
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const new_lhs_lock = self.register_manager.lockReg(lhs_reg);
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const rhs_reg = if (rhs_is_register)
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rhs.register
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else
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try self.register_manager.allocReg(null, gp);
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const new_rhs_lock = self.register_manager.lockReg(rhs_reg);
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defer if (new_rhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_regs = try self.register_manager.allocRegs(2, .{ null, null }, gp);
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const dest_regs_locks = self.register_manager.lockRegsAssumeUnused(2, dest_regs);
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defer for (dest_regs_locks) |reg| {
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self.register_manager.unlockReg(reg);
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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.{ .ty = rhs_ty, .bind = rhs_bind, .class = gp, .reg = &rhs_reg },
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};
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const rdlo = dest_regs[0];
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const rdhi = dest_regs[1];
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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const truncated_reg = try self.register_manager.allocReg(null, gp);
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const truncated_reg_lock = self.register_manager.lockRegAssumeUnused(truncated_reg);
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defer self.register_manager.unlockReg(truncated_reg_lock);
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &rdhi },
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &rdlo },
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &truncated_reg },
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};
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try self.allocRegs(
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&read_args,
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&write_args,
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null,
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);
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_ = try self.addInst(.{
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.tag = base_tag,
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@ -2933,172 +2907,10 @@ fn allocRegs(
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}
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}
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/// Don't call this function directly. Use binOp instead.
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/// Wrapper around allocRegs and addInst tailored for specific Mir
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/// instructions which are binary operations acting on two registers
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///
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/// Calling this function signals an intention to generate a Mir
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/// instruction of the form
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///
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/// op dest, lhs, rhs
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///
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/// Asserts that generating an instruction of that form is possible.
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fn binOpRegister(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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metadata: ?BinOpMetadata,
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) !MCValue {
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var lhs_reg: Register = undefined;
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var rhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const lhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.lhs }
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else
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ReadArg.Bind{ .mcv = lhs };
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const rhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.rhs }
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else
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ReadArg.Bind{ .mcv = rhs };
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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.{ .ty = rhs_ty, .bind = rhs_bind, .class = gp, .reg = &rhs_reg },
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};
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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try self.allocRegs(
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&read_args,
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&write_args,
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if (metadata) |md| .{
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.corresponding_inst = md.inst,
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.operand_mapping = &.{ 0, 1 },
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} else null,
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);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add,
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.adds,
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.sub,
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.subs,
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.@"and",
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.orr,
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.eor,
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=> .{ .rr_op = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.op = Instruction.Operand.reg(rhs_reg, Instruction.Operand.Shift.none),
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} },
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.lsl,
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.asr,
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.lsr,
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=> .{ .rr_shift = .{
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.rd = dest_reg,
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.rm = lhs_reg,
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.shift_amount = Instruction.ShiftAmount.reg(rhs_reg),
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} },
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.mul,
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.smulbb,
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=> .{ .rrr = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.rm = rhs_reg,
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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/// Don't call this function directly. Use binOp instead.
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///
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/// Calling this function signals an intention to generate a Mir
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/// instruction of the form
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///
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/// op dest, lhs, #rhs_imm
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///
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/// Set lhs_and_rhs_swapped to true iff inst.bin_op.lhs corresponds to
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/// rhs and vice versa. This parameter is only used when maybe_inst !=
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/// null.
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///
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/// Asserts that generating an instruction of that form is possible.
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fn binOpImmediate(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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lhs_and_rhs_swapped: bool,
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metadata: ?BinOpMetadata,
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) !MCValue {
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var lhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const lhs_bind = blk: {
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if (metadata) |md| {
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const inst = if (lhs_and_rhs_swapped) md.rhs else md.lhs;
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break :blk ReadArg.Bind{ .inst = inst };
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} else {
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break :blk ReadArg.Bind{ .mcv = lhs };
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}
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};
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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};
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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const operand_mapping: []const Liveness.OperandInt = if (lhs_and_rhs_swapped) &.{1} else &.{0};
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try self.allocRegs(
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&read_args,
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&write_args,
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if (metadata) |md| .{
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.corresponding_inst = md.inst,
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.operand_mapping = operand_mapping,
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} else null,
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);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add,
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.adds,
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.sub,
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.subs,
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.@"and",
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.orr,
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.eor,
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=> .{ .rr_op = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.op = Instruction.Operand.fromU32(rhs.immediate).?,
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} },
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.lsl,
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.asr,
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.lsr,
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=> .{ .rr_shift = .{
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.rd = dest_reg,
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.rm = lhs_reg,
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.shift_amount = Instruction.ShiftAmount.imm(@intCast(u5, rhs.immediate)),
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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/// TODO
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/// Returns the destination register
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fn binOpRegisterNew(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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@ -3167,7 +2979,11 @@ fn binOpRegisterNew(
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return MCValue{ .register = dest_reg };
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}
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/// TODO
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/// Wrapper around allocRegs and addInst tailored for specific Mir
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/// instructions which are binary operations acting on a register and
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/// an immediate
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///
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/// Returns the destination register
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fn binOpImmediateNew(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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@ -3228,12 +3044,6 @@ fn binOpImmediateNew(
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return MCValue{ .register = dest_reg };
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}
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const BinOpMetadata = struct {
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inst: Air.Inst.Index,
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lhs: Air.Inst.Ref,
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rhs: Air.Inst.Ref,
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};
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fn addSub(
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self: *Self,
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tag: Air.Inst.Tag,
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