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stage2 ARM: extract remaining operations out of binOp
This commit is contained in:
joachimschmidt557
parent
fdb2c80bdc
commit
95b8a5f157
@ -1407,8 +1407,6 @@ fn airBinOp(self: *Self, inst: Air.Inst.Index, tag: Air.Inst.Tag) !void {
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const lhs_bind: ReadArg.Bind = .{ .inst = bin_op.lhs };
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const rhs_bind: ReadArg.Bind = .{ .inst = bin_op.rhs };
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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break :result switch (tag) {
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.add => try self.addSub(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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@ -1427,11 +1425,24 @@ fn airBinOp(self: *Self, inst: Air.Inst.Index, tag: Air.Inst.Tag) !void {
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.mod => try self.modulo(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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else => try self.binOp(tag, lhs, rhs, lhs_ty, rhs_ty, BinOpMetadata{
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.lhs = bin_op.lhs,
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.rhs = bin_op.rhs,
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.inst = inst,
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}),
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.addwrap => try self.wrappingArithmetic(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.subwrap => try self.wrappingArithmetic(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.mulwrap => try self.wrappingArithmetic(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.bit_and => try self.bitwise(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.bit_or => try self.bitwise(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.xor => try self.bitwise(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.shl_exact => try self.shiftExact(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.shr_exact => try self.shiftExact(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.shl => try self.shiftNormal(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.shr => try self.shiftNormal(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.bool_and => try self.booleanOp(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.bool_or => try self.booleanOp(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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else => unreachable,
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};
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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@ -1440,19 +1451,15 @@ fn airBinOp(self: *Self, inst: Air.Inst.Index, tag: Air.Inst.Tag) !void {
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fn airPtrArithmetic(self: *Self, inst: Air.Inst.Index, tag: Air.Inst.Tag) !void {
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const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
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const bin_op = self.air.extraData(Air.Bin, ty_pl.payload).data;
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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const rhs_ty = self.air.typeOf(bin_op.rhs);
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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try self.binOp(tag, lhs, rhs, lhs_ty, rhs_ty, BinOpMetadata{
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.lhs = bin_op.lhs,
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.rhs = bin_op.rhs,
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.inst = inst,
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});
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const lhs_bind: ReadArg.Bind = .{ .inst = bin_op.lhs };
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const rhs_bind: ReadArg.Bind = .{ .inst = bin_op.rhs };
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break :result try self.ptrArithmetic(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst);
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -2247,7 +2254,11 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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},
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else => {
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const dest = try self.allocRegOrMem(inst, true);
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const addr = try self.binOp(.ptr_add, base_mcv, index_mcv, slice_ptr_field_type, Type.usize, null);
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const base_bind: ReadArg.Bind = .{ .mcv = base_mcv };
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const index_bind: ReadArg.Bind = .{ .mcv = index_mcv };
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const addr = try self.ptrArithmetic(.ptr_add, base_bind, index_bind, slice_ptr_field_type, Type.usize, null);
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try self.load(dest, addr, slice_ptr_field_type);
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break :result dest;
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@ -2262,12 +2273,15 @@ fn airSliceElemPtr(self: *Self, inst: Air.Inst.Index) !void {
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const extra = self.air.extraData(Air.Bin, ty_pl.payload).data;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const slice_mcv = try self.resolveInst(extra.lhs);
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const index_mcv = try self.resolveInst(extra.rhs);
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const base_mcv = slicePtr(slice_mcv);
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const slice_ty = self.air.typeOf(extra.lhs);
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const base_bind: ReadArg.Bind = .{ .mcv = base_mcv };
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const index_bind: ReadArg.Bind = .{ .inst = extra.rhs };
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const addr = try self.binOp(.ptr_add, base_mcv, index_mcv, slice_ty, Type.usize, null);
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const slice_ty = self.air.typeOf(extra.lhs);
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const index_ty = self.air.typeOf(extra.rhs);
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const addr = try self.ptrArithmetic(.ptr_add, base_bind, index_bind, slice_ty, index_ty, null);
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break :result addr;
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};
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return self.finishAir(inst, result, .{ extra.lhs, extra.rhs, .none });
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@ -2290,12 +2304,13 @@ fn airPtrElemPtr(self: *Self, inst: Air.Inst.Index) !void {
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const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
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const extra = self.air.extraData(Air.Bin, ty_pl.payload).data;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const ptr_mcv = try self.resolveInst(extra.lhs);
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const index_mcv = try self.resolveInst(extra.rhs);
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const ptr_bind: ReadArg.Bind = .{ .inst = extra.lhs };
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const index_bind: ReadArg.Bind = .{ .inst = extra.rhs };
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const ptr_ty = self.air.typeOf(extra.lhs);
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const index_ty = self.air.typeOf(extra.rhs);
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const addr = try self.binOp(.ptr_add, ptr_mcv, index_mcv, ptr_ty, Type.usize, null);
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const addr = try self.ptrArithmetic(.ptr_add, ptr_bind, index_bind, ptr_ty, index_ty, null);
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break :result addr;
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};
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return self.finishAir(inst, result, .{ extra.lhs, extra.rhs, .none });
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@ -3219,240 +3234,6 @@ const BinOpMetadata = struct {
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rhs: Air.Inst.Ref,
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};
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/// For all your binary operation needs, this function will generate
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/// the corresponding Mir instruction(s). Returns the location of the
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/// result.
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///
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/// If the binary operation itself happens to be an Air instruction,
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/// pass the corresponding index in the inst parameter. That helps
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/// this function do stuff like reusing operands.
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///
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/// This function does not do any lowering to Mir itself, but instead
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/// looks at the lhs and rhs and determines which kind of lowering
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/// would be best suitable and then delegates the lowering to other
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/// functions.
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fn binOp(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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metadata: ?BinOpMetadata,
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) InnerError!MCValue {
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switch (tag) {
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.addwrap,
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.subwrap,
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.mulwrap,
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=> {
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const base_tag: Air.Inst.Tag = switch (tag) {
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.addwrap => .add,
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.subwrap => .sub,
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.mulwrap => .mul,
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else => unreachable,
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};
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const lhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.lhs }
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else
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ReadArg.Bind{ .mcv = lhs };
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const rhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.rhs }
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else
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ReadArg.Bind{ .mcv = rhs };
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// Generate an add/sub/mul
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const maybe_inst: ?Air.Inst.Index = if (metadata) |md| md.inst else null;
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const result = try self.addSub(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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// Truncate if necessary
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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const result_reg = result.register;
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if (int_info.bits < 32) {
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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return result;
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} else return result;
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.bit_and,
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.bit_or,
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.xor,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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const lhs_immediate_ok = lhs == .immediate and Instruction.Operand.fromU32(lhs.immediate) != null;
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const rhs_immediate_ok = rhs == .immediate and Instruction.Operand.fromU32(rhs.immediate) != null;
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.bit_and => .@"and",
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.bit_or => .orr,
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.xor => .eor,
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(mir_tag, lhs, rhs, lhs_ty, false, metadata);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediate(mir_tag, rhs, lhs, rhs_ty, true, metadata);
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} else {
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return try self.binOpRegister(mir_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.shl_exact,
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.shr_exact,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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const rhs_immediate_ok = rhs == .immediate;
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.shl_exact => .lsl,
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.shr_exact => switch (lhs_ty.intInfo(self.target.*).signedness) {
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.signed => Mir.Inst.Tag.asr,
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.unsigned => Mir.Inst.Tag.lsr,
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},
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(mir_tag, lhs, rhs, lhs_ty, false, metadata);
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} else {
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return try self.binOpRegister(mir_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.shl,
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.shr,
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=> {
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const base_tag: Air.Inst.Tag = switch (tag) {
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.shl => .shl_exact,
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.shr => .shr_exact,
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else => unreachable,
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};
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// Generate a shl_exact/shr_exact
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const result = try self.binOp(base_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
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// Truncate if necessary
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switch (tag) {
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.shr => return result,
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.shl => switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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const result_reg = result.register;
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if (int_info.bits < 32) {
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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return result;
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} else return result;
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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},
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else => unreachable,
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}
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},
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.bool_and,
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.bool_or,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Bool => {
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const lhs_immediate_ok = lhs == .immediate;
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const rhs_immediate_ok = rhs == .immediate;
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.bool_and => .@"and",
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.bool_or => .orr,
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(mir_tag, lhs, rhs, lhs_ty, false, metadata);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediate(mir_tag, rhs, lhs, rhs_ty, true, metadata);
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} else {
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return try self.binOpRegister(mir_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
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}
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},
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else => unreachable,
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}
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},
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.ptr_add,
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.ptr_sub,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Pointer => {
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const ptr_ty = lhs_ty;
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const elem_ty = switch (ptr_ty.ptrSize()) {
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.One => ptr_ty.childType().childType(), // ptr to array, so get array element type
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else => ptr_ty.childType(),
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};
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const elem_size = @intCast(u32, elem_ty.abiSize(self.target.*));
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if (elem_size == 1) {
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const base_tag: Mir.Inst.Tag = switch (tag) {
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.ptr_add => .add,
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.ptr_sub => .sub,
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else => unreachable,
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};
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return try self.binOpRegister(base_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
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} else {
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// convert the offset into a byte offset by
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// multiplying it with elem_size
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const rhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.rhs }
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else
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ReadArg.Bind{ .mcv = rhs };
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const imm_bind = ReadArg.Bind{ .mcv = .{ .immediate = elem_size } };
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const offset = try self.mul(rhs_bind, imm_bind, Type.usize, Type.usize, null);
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const addr = try self.binOp(tag, lhs, offset, Type.initTag(.manyptr_u8), Type.usize, null);
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return addr;
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}
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},
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else => unreachable,
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}
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},
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else => unreachable,
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}
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}
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fn addSub(
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self: *Self,
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tag: Air.Inst.Tag,
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@ -3713,6 +3494,248 @@ fn modulo(
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}
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}
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fn wrappingArithmetic(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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const base_tag: Air.Inst.Tag = switch (tag) {
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.addwrap => .add,
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.subwrap => .sub,
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.mulwrap => .mul,
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else => unreachable,
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};
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// Generate an add/sub/mul
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const result = try self.addSub(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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// Truncate if necessary
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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const result_reg = result.register;
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if (int_info.bits < 32) {
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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return result;
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} else return result;
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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}
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fn bitwise(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
|
||||
assert(lhs_ty.eql(rhs_ty, mod));
|
||||
const int_info = lhs_ty.intInfo(self.target.*);
|
||||
if (int_info.bits <= 32) {
|
||||
const lhs_immediate = try lhs_bind.resolveToImmediate(self);
|
||||
const rhs_immediate = try rhs_bind.resolveToImmediate(self);
|
||||
|
||||
const lhs_immediate_ok = if (lhs_immediate) |imm| Instruction.Operand.fromU32(imm) != null else false;
|
||||
const rhs_immediate_ok = if (rhs_immediate) |imm| Instruction.Operand.fromU32(imm) != null else false;
|
||||
|
||||
const mir_tag: Mir.Inst.Tag = switch (tag) {
|
||||
.bit_and => .@"and",
|
||||
.bit_or => .orr,
|
||||
.xor => .eor,
|
||||
else => unreachable,
|
||||
};
|
||||
|
||||
if (rhs_immediate_ok) {
|
||||
return try self.binOpImmediateNew(mir_tag, lhs_bind, rhs_immediate.?, lhs_ty, false, maybe_inst);
|
||||
} else if (lhs_immediate_ok) {
|
||||
// swap lhs and rhs
|
||||
return try self.binOpImmediateNew(mir_tag, rhs_bind, lhs_immediate.?, rhs_ty, true, maybe_inst);
|
||||
} else {
|
||||
return try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
|
||||
}
|
||||
} else {
|
||||
return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
|
||||
}
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn shiftExact(
|
||||
self: *Self,
|
||||
tag: Air.Inst.Tag,
|
||||
lhs_bind: ReadArg.Bind,
|
||||
rhs_bind: ReadArg.Bind,
|
||||
lhs_ty: Type,
|
||||
rhs_ty: Type,
|
||||
maybe_inst: ?Air.Inst.Index,
|
||||
) InnerError!MCValue {
|
||||
switch (lhs_ty.zigTypeTag()) {
|
||||
.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
|
||||
.Int => {
|
||||
const int_info = lhs_ty.intInfo(self.target.*);
|
||||
if (int_info.bits <= 32) {
|
||||
const rhs_immediate = try rhs_bind.resolveToImmediate(self);
|
||||
|
||||
const mir_tag: Mir.Inst.Tag = switch (tag) {
|
||||
.shl_exact => .lsl,
|
||||
.shr_exact => switch (lhs_ty.intInfo(self.target.*).signedness) {
|
||||
.signed => Mir.Inst.Tag.asr,
|
||||
.unsigned => Mir.Inst.Tag.lsr,
|
||||
},
|
||||
else => unreachable,
|
||||
};
|
||||
|
||||
if (rhs_immediate) |imm| {
|
||||
return try self.binOpImmediateNew(mir_tag, lhs_bind, imm, lhs_ty, false, maybe_inst);
|
||||
} else {
|
||||
return try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
|
||||
}
|
||||
} else {
|
||||
return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
|
||||
}
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn shiftNormal(
|
||||
self: *Self,
|
||||
tag: Air.Inst.Tag,
|
||||
lhs_bind: ReadArg.Bind,
|
||||
rhs_bind: ReadArg.Bind,
|
||||
lhs_ty: Type,
|
||||
rhs_ty: Type,
|
||||
maybe_inst: ?Air.Inst.Index,
|
||||
) InnerError!MCValue {
|
||||
const base_tag: Air.Inst.Tag = switch (tag) {
|
||||
.shl => .shl_exact,
|
||||
.shr => .shr_exact,
|
||||
else => unreachable,
|
||||
};
|
||||
|
||||
// Generate a shl_exact/shr_exact
|
||||
const result = try self.shiftExact(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
|
||||
|
||||
// Truncate if necessary
|
||||
switch (tag) {
|
||||
.shr => return result,
|
||||
.shl => switch (lhs_ty.zigTypeTag()) {
|
||||
.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
|
||||
.Int => {
|
||||
const int_info = lhs_ty.intInfo(self.target.*);
|
||||
if (int_info.bits <= 32) {
|
||||
const result_reg = result.register;
|
||||
|
||||
if (int_info.bits < 32) {
|
||||
try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
|
||||
return result;
|
||||
} else return result;
|
||||
} else {
|
||||
return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
|
||||
}
|
||||
},
|
||||
else => unreachable,
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn booleanOp(
|
||||
self: *Self,
|
||||
tag: Air.Inst.Tag,
|
||||
lhs_bind: ReadArg.Bind,
|
||||
rhs_bind: ReadArg.Bind,
|
||||
lhs_ty: Type,
|
||||
rhs_ty: Type,
|
||||
maybe_inst: ?Air.Inst.Index,
|
||||
) InnerError!MCValue {
|
||||
switch (lhs_ty.zigTypeTag()) {
|
||||
.Bool => {
|
||||
const lhs_immediate = try lhs_bind.resolveToImmediate(self);
|
||||
const rhs_immediate = try rhs_bind.resolveToImmediate(self);
|
||||
|
||||
const mir_tag: Mir.Inst.Tag = switch (tag) {
|
||||
.bool_and => .@"and",
|
||||
.bool_or => .orr,
|
||||
else => unreachable,
|
||||
};
|
||||
|
||||
if (rhs_immediate) |imm| {
|
||||
return try self.binOpImmediateNew(mir_tag, lhs_bind, imm, lhs_ty, false, maybe_inst);
|
||||
} else if (lhs_immediate) |imm| {
|
||||
// swap lhs and rhs
|
||||
return try self.binOpImmediateNew(mir_tag, rhs_bind, imm, rhs_ty, true, maybe_inst);
|
||||
} else {
|
||||
return try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
|
||||
}
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn ptrArithmetic(
|
||||
self: *Self,
|
||||
tag: Air.Inst.Tag,
|
||||
lhs_bind: ReadArg.Bind,
|
||||
rhs_bind: ReadArg.Bind,
|
||||
lhs_ty: Type,
|
||||
rhs_ty: Type,
|
||||
maybe_inst: ?Air.Inst.Index,
|
||||
) InnerError!MCValue {
|
||||
switch (lhs_ty.zigTypeTag()) {
|
||||
.Pointer => {
|
||||
const mod = self.bin_file.options.module.?;
|
||||
assert(rhs_ty.eql(Type.usize, mod));
|
||||
|
||||
const ptr_ty = lhs_ty;
|
||||
const elem_ty = switch (ptr_ty.ptrSize()) {
|
||||
.One => ptr_ty.childType().childType(), // ptr to array, so get array element type
|
||||
else => ptr_ty.childType(),
|
||||
};
|
||||
const elem_size = @intCast(u32, elem_ty.abiSize(self.target.*));
|
||||
|
||||
const base_tag: Air.Inst.Tag = switch (tag) {
|
||||
.ptr_add => .add,
|
||||
.ptr_sub => .sub,
|
||||
else => unreachable,
|
||||
};
|
||||
|
||||
if (elem_size == 1) {
|
||||
return try self.addSub(base_tag, lhs_bind, rhs_bind, Type.usize, Type.usize, maybe_inst);
|
||||
} else {
|
||||
// convert the offset into a byte offset by
|
||||
// multiplying it with elem_size
|
||||
const imm_bind = ReadArg.Bind{ .mcv = .{ .immediate = elem_size } };
|
||||
|
||||
const offset = try self.mul(rhs_bind, imm_bind, Type.usize, Type.usize, null);
|
||||
const offset_bind = ReadArg.Bind{ .mcv = offset };
|
||||
|
||||
const addr = try self.addSub(base_tag, lhs_bind, offset_bind, Type.usize, Type.usize, null);
|
||||
return addr;
|
||||
}
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn genLdrRegister(self: *Self, dest_reg: Register, addr_reg: Register, ty: Type) !void {
|
||||
const abi_size = ty.abiSize(self.target.*);
|
||||
|
||||
@ -4614,7 +4637,7 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
|
||||
if (else_value == .dead)
|
||||
continue;
|
||||
// The instruction is only overridden in the else branch.
|
||||
var i: usize = self.branch_stack.items.len - 2;
|
||||
var i: usize = self.branch_stack.items.len - 1;
|
||||
while (true) {
|
||||
i -= 1; // If this overflows, the question is: why wasn't the instruction marked dead?
|
||||
if (self.branch_stack.items[i].inst_table.get(else_key)) |mcv| {
|
||||
@ -4641,7 +4664,7 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
|
||||
if (then_value == .dead)
|
||||
continue;
|
||||
const parent_mcv = blk: {
|
||||
var i: usize = self.branch_stack.items.len - 2;
|
||||
var i: usize = self.branch_stack.items.len - 1;
|
||||
while (true) {
|
||||
i -= 1;
|
||||
if (self.branch_stack.items[i].inst_table.get(then_key)) |mcv| {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user