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https://github.com/ziglang/zig.git
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stage2 ARM: extract mul, div, and mod out of binOp
This commit is contained in:
joachimschmidt557
parent
ed4be06883
commit
fdb2c80bdc
@ -1410,16 +1410,29 @@ fn airBinOp(self: *Self, inst: Air.Inst.Index, tag: Air.Inst.Tag) !void {
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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switch (tag) {
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.add,
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.sub,
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=> break :result try self.addSub(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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else => break :result try self.binOp(tag, lhs, rhs, lhs_ty, rhs_ty, BinOpMetadata{
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break :result switch (tag) {
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.add => try self.addSub(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.sub => try self.addSub(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.mul => try self.mul(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.div_float => try self.divFloat(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.div_trunc => try self.div(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.div_floor => try self.div(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.div_exact => try self.divExact(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.rem => try self.rem(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.mod => try self.modulo(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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else => try self.binOp(tag, lhs, rhs, lhs_ty, rhs_ty, BinOpMetadata{
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.lhs = bin_op.lhs,
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.rhs = bin_op.rhs,
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.inst = inst,
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}),
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}
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};
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -3228,141 +3241,6 @@ fn binOp(
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metadata: ?BinOpMetadata,
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) InnerError!MCValue {
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switch (tag) {
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.mul => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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// TODO add optimisations for multiplication
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// with immediates, for example a * 2 can be
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// lowered to a << 1
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return try self.binOpRegister(.mul, lhs, rhs, lhs_ty, rhs_ty, metadata);
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.div_float => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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else => unreachable,
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}
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},
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.div_trunc, .div_floor => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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switch (int_info.signedness) {
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.signed => {
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return self.fail("TODO ARM signed integer division", .{});
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},
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.unsigned => {
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switch (rhs) {
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.immediate => |imm| {
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if (std.math.isPowerOfTwo(imm)) {
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const shift = MCValue{ .immediate = std.math.log2_int(u32, imm) };
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return try self.binOp(.shr, lhs, shift, lhs_ty, rhs_ty, metadata);
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} else {
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return self.fail("TODO ARM integer division by constants", .{});
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}
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},
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else => return self.fail("TODO ARM integer division", .{}),
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}
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},
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}
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} else {
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return self.fail("TODO ARM integer division for integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.div_exact => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => return self.fail("TODO ARM div_exact", .{}),
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else => unreachable,
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}
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},
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.rem => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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switch (int_info.signedness) {
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.signed => {
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return self.fail("TODO ARM signed integer mod", .{});
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},
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.unsigned => {
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switch (rhs) {
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.immediate => |imm| {
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if (std.math.isPowerOfTwo(imm)) {
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const log2 = std.math.log2_int(u32, imm);
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var lhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const lhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.lhs }
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else
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ReadArg.Bind{ .mcv = lhs };
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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};
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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try self.allocRegs(
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&read_args,
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&write_args,
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if (metadata) |md| .{
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.corresponding_inst = md.inst,
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.operand_mapping = &.{0},
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} else null,
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);
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try self.truncRegister(lhs_reg, dest_reg, int_info.signedness, log2);
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return MCValue{ .register = dest_reg };
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} else {
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return self.fail("TODO ARM integer mod by constants", .{});
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}
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},
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else => return self.fail("TODO ARM integer mod", .{}),
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}
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},
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}
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} else {
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return self.fail("TODO ARM integer division for integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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},
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.mod => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => return self.fail("TODO ARM mod", .{}),
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else => unreachable,
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}
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},
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.addwrap,
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.subwrap,
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.mulwrap,
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@ -3557,7 +3435,13 @@ fn binOp(
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} else {
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// convert the offset into a byte offset by
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// multiplying it with elem_size
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const offset = try self.binOp(.mul, rhs, .{ .immediate = elem_size }, Type.usize, Type.usize, null);
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const rhs_bind = if (metadata) |md|
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ReadArg.Bind{ .inst = md.rhs }
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else
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ReadArg.Bind{ .mcv = rhs };
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const imm_bind = ReadArg.Bind{ .mcv = .{ .immediate = elem_size } };
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const offset = try self.mul(rhs_bind, imm_bind, Type.usize, Type.usize, null);
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const addr = try self.binOp(tag, lhs, offset, Type.initTag(.manyptr_u8), Type.usize, null);
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return addr;
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}
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@ -3626,6 +3510,209 @@ fn addSub(
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}
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}
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fn mul(
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self: *Self,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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// TODO add optimisations for multiplication
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// with immediates, for example a * 2 can be
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// lowered to a << 1
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return try self.binOpRegisterNew(.mul, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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}
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fn divFloat(
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self: *Self,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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_ = lhs_bind;
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_ = rhs_bind;
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_ = lhs_ty;
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_ = rhs_ty;
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_ = maybe_inst;
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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else => unreachable,
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}
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}
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fn div(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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_ = tag;
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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switch (int_info.signedness) {
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.signed => {
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return self.fail("TODO ARM signed integer division", .{});
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},
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.unsigned => {
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const rhs_immediate = try rhs_bind.resolveToImmediate(self);
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if (rhs_immediate) |imm| {
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if (std.math.isPowerOfTwo(imm)) {
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const shift = std.math.log2_int(u32, imm);
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return try self.binOpImmediateNew(.lsr, lhs_bind, shift, lhs_ty, false, maybe_inst);
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} else {
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return self.fail("TODO ARM integer division by constants", .{});
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}
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} else {
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return self.fail("TODO ARM integer division", .{});
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}
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},
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}
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} else {
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return self.fail("TODO ARM integer division for integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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}
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fn divExact(
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self: *Self,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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_ = lhs_bind;
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_ = rhs_bind;
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_ = lhs_ty;
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_ = rhs_ty;
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_ = maybe_inst;
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => return self.fail("TODO ARM div_exact", .{}),
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else => unreachable,
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}
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}
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fn rem(
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self: *Self,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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switch (int_info.signedness) {
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.signed => {
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return self.fail("TODO ARM signed integer mod", .{});
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},
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.unsigned => {
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const rhs_immediate = try rhs_bind.resolveToImmediate(self);
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if (rhs_immediate) |imm| {
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if (std.math.isPowerOfTwo(imm)) {
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const log2 = std.math.log2_int(u32, imm);
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var lhs_reg: Register = undefined;
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var dest_reg: Register = undefined;
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const read_args = [_]ReadArg{
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.{ .ty = lhs_ty, .bind = lhs_bind, .class = gp, .reg = &lhs_reg },
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};
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const write_args = [_]WriteArg{
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.{ .ty = lhs_ty, .bind = .none, .class = gp, .reg = &dest_reg },
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};
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try self.allocRegs(
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&read_args,
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&write_args,
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if (maybe_inst) |inst| .{
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.corresponding_inst = inst,
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.operand_mapping = &.{0},
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} else null,
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);
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try self.truncRegister(lhs_reg, dest_reg, int_info.signedness, log2);
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return MCValue{ .register = dest_reg };
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} else {
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return self.fail("TODO ARM integer mod by constants", .{});
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}
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} else {
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return self.fail("TODO ARM integer mod", .{});
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}
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},
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}
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} else {
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return self.fail("TODO ARM integer division for integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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}
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fn modulo(
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self: *Self,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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_ = lhs_bind;
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_ = rhs_bind;
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_ = lhs_ty;
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_ = rhs_ty;
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_ = maybe_inst;
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => return self.fail("TODO ARM mod", .{}),
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else => unreachable,
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}
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}
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fn genLdrRegister(self: *Self, dest_reg: Register, addr_reg: Register, ty: Type) !void {
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const abi_size = ty.abiSize(self.target.*);
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