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https://github.com/ziglang/zig.git
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stage2 ARM: pass stack arguments in opposite order
Earlier arguments have a smaller address (i.e. towards the bottom of the stack)
This commit is contained in:
joachimschmidt557
parent
7e07f3d4f9
commit
4c5156544b
@ -332,7 +332,7 @@ pub fn generate(
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};
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for (function.dbg_arg_relocs.items) |reloc| {
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try function.genArgDbgInfo(reloc.inst, reloc.index, call_info.stack_byte_count);
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try function.genArgDbgInfo(reloc.inst, reloc.index);
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}
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var mir = Mir{
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@ -351,7 +351,8 @@ pub fn generate(
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.prev_di_pc = 0,
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.prev_di_line = module_fn.lbrace_line,
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.prev_di_column = module_fn.lbrace_column,
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.prologue_stack_space = call_info.stack_byte_count + function.saved_regs_stack_space,
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.stack_size = function.max_end_stack,
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.saved_regs_stack_space = function.saved_regs_stack_space,
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};
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defer emit.deinit();
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@ -464,6 +465,7 @@ fn gen(self: *Self) !void {
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const total_stack_size = self.max_end_stack + self.saved_regs_stack_space;
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const aligned_total_stack_end = mem.alignForwardGeneric(u32, total_stack_size, self.stack_align);
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const stack_size = aligned_total_stack_end - self.saved_regs_stack_space;
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self.max_end_stack = stack_size;
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if (Instruction.Operand.fromU32(stack_size)) |op| {
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self.mir_instructions.set(sub_reloc, .{
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.tag = .sub,
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@ -1812,7 +1814,7 @@ fn errUnionErr(self: *Self, error_union_mcv: MCValue, error_union_ty: Type) !MCV
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switch (error_union_mcv) {
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.register => return self.fail("TODO errUnionErr for registers", .{}),
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.stack_argument_offset => |off| {
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return MCValue{ .stack_argument_offset = off - err_offset };
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return MCValue{ .stack_argument_offset = off + err_offset };
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},
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.stack_offset => |off| {
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return MCValue{ .stack_offset = off - err_offset };
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@ -1849,7 +1851,7 @@ fn errUnionPayload(self: *Self, error_union_mcv: MCValue, error_union_ty: Type)
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switch (error_union_mcv) {
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.register => return self.fail("TODO errUnionPayload for registers", .{}),
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.stack_argument_offset => |off| {
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return MCValue{ .stack_argument_offset = off - payload_offset };
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return MCValue{ .stack_argument_offset = off + payload_offset };
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},
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.stack_offset => |off| {
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return MCValue{ .stack_offset = off - payload_offset };
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@ -1983,7 +1985,7 @@ fn airSliceLen(self: *Self, inst: Air.Inst.Index) !void {
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.dead, .unreach => unreachable,
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.register => unreachable, // a slice doesn't fit in one register
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.stack_argument_offset => |off| {
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break :result MCValue{ .stack_argument_offset = off - 4 };
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break :result MCValue{ .stack_argument_offset = off + 4 };
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},
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.stack_offset => |off| {
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break :result MCValue{ .stack_offset = off - 4 };
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@ -2507,7 +2509,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
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switch (mcv) {
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.dead, .unreach => unreachable,
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.stack_argument_offset => |off| {
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break :result MCValue{ .stack_argument_offset = off - struct_field_offset };
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break :result MCValue{ .stack_argument_offset = off + struct_field_offset };
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},
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.stack_offset => |off| {
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break :result MCValue{ .stack_offset = off - struct_field_offset };
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@ -3369,9 +3371,7 @@ fn addDbgInfoTypeReloc(self: *Self, ty: Type) error{OutOfMemory}!void {
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}
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}
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fn genArgDbgInfo(self: *Self, inst: Air.Inst.Index, arg_index: u32, stack_byte_count: u32) error{OutOfMemory}!void {
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const prologue_stack_space = stack_byte_count + self.saved_regs_stack_space;
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fn genArgDbgInfo(self: *Self, inst: Air.Inst.Index, arg_index: u32) error{OutOfMemory}!void {
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const mcv = self.args[arg_index];
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const ty = self.air.instructions.items(.data)[inst].ty;
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const name = self.mod_fn.getParamName(self.bin_file.options.module.?, arg_index);
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@ -3404,7 +3404,7 @@ fn genArgDbgInfo(self: *Self, inst: Air.Inst.Index, arg_index: u32, stack_byte_c
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// const abi_size = @intCast(u32, ty.abiSize(self.target.*));
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const adjusted_stack_offset = switch (mcv) {
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.stack_offset => |offset| -@intCast(i32, offset),
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.stack_argument_offset => |offset| @intCast(i32, prologue_stack_space - offset),
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.stack_argument_offset => |offset| @intCast(i32, self.saved_regs_stack_space + offset),
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else => unreachable,
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};
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@ -3559,7 +3559,7 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
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.stack_offset => unreachable,
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.stack_argument_offset => |offset| try self.genSetStackArgument(
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arg_ty,
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info.stack_byte_count - offset,
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offset,
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arg_mcv,
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),
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else => unreachable,
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@ -5653,8 +5653,8 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type) !CallMCValues {
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if (ty.abiAlignment(self.target.*) == 8)
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nsaa = std.mem.alignForwardGeneric(u32, nsaa, 8);
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nsaa += param_size;
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result.args[i] = .{ .stack_argument_offset = nsaa };
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nsaa += param_size;
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}
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}
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@ -5687,9 +5687,11 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type) !CallMCValues {
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for (param_types) |ty, i| {
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if (ty.abiSize(self.target.*) > 0) {
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const param_size = @intCast(u32, ty.abiSize(self.target.*));
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const param_alignment = ty.abiAlignment(self.target.*);
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stack_offset = std.mem.alignForwardGeneric(u32, stack_offset, ty.abiAlignment(self.target.*)) + param_size;
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stack_offset = std.mem.alignForwardGeneric(u32, stack_offset, param_alignment);
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result.args[i] = .{ .stack_argument_offset = stack_offset };
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stack_offset += param_size;
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} else {
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result.args[i] = .{ .none = {} };
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}
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@ -33,9 +33,13 @@ prev_di_column: u32,
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/// Relative to the beginning of `code`.
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prev_di_pc: usize,
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/// The amount of stack space consumed by all stack arguments as well
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/// as the saved callee-saved registers
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prologue_stack_space: u32,
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/// The amount of stack space consumed by the saved callee-saved
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/// registers in bytes
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saved_regs_stack_space: u32,
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/// The final stack frame size of the function (already aligned to the
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/// respective stack alignment). Does not include prologue stack space.
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stack_size: u32,
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/// The branch type of every branch
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branch_types: std.AutoHashMapUnmanaged(Mir.Inst.Index, BranchType) = .{},
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@ -500,14 +504,15 @@ fn mirLoadStackArgument(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const cond = emit.mir.instructions.items(.cond)[inst];
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const r_stack_offset = emit.mir.instructions.items(.data)[inst].r_stack_offset;
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const rt = r_stack_offset.rt;
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const raw_offset = emit.prologue_stack_space - r_stack_offset.stack_offset;
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const raw_offset = emit.stack_size + emit.saved_regs_stack_space + r_stack_offset.stack_offset;
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switch (tag) {
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.ldr_ptr_stack_argument => {
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const operand = Instruction.Operand.fromU32(raw_offset) orelse
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return emit.fail("TODO mirLoadStack larger offsets", .{});
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try emit.writeInstruction(Instruction.add(cond, r_stack_offset.rt, .fp, operand));
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try emit.writeInstruction(Instruction.add(cond, rt, .sp, operand));
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},
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.ldr_stack_argument,
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.ldrb_stack_argument,
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@ -516,23 +521,11 @@ fn mirLoadStackArgument(emit: *Emit, inst: Mir.Inst.Index) !void {
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break :blk Instruction.Offset.imm(@intCast(u12, raw_offset));
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} else return emit.fail("TODO mirLoadStack larger offsets", .{});
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const ldr = switch (tag) {
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.ldr_stack_argument => &Instruction.ldr,
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.ldrb_stack_argument => &Instruction.ldrb,
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switch (tag) {
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.ldr_stack_argument => try emit.writeInstruction(Instruction.ldr(cond, rt, .sp, .{ .offset = offset })),
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.ldrb_stack_argument => try emit.writeInstruction(Instruction.ldrb(cond, rt, .sp, .{ .offset = offset })),
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else => unreachable,
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};
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const ldr_workaround = switch (builtin.zig_backend) {
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.stage1 => ldr.*,
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else => ldr,
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};
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try emit.writeInstruction(ldr_workaround(
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cond,
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r_stack_offset.rt,
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.fp,
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.{ .offset = offset },
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));
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}
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},
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.ldrh_stack_argument,
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.ldrsb_stack_argument,
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@ -542,24 +535,12 @@ fn mirLoadStackArgument(emit: *Emit, inst: Mir.Inst.Index) !void {
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break :blk Instruction.ExtraLoadStoreOffset.imm(@intCast(u8, raw_offset));
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} else return emit.fail("TODO mirLoadStack larger offsets", .{});
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const ldr = switch (tag) {
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.ldrh_stack_argument => &Instruction.ldrh,
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.ldrsb_stack_argument => &Instruction.ldrsb,
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.ldrsh_stack_argument => &Instruction.ldrsh,
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switch (tag) {
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.ldrh_stack_argument => try emit.writeInstruction(Instruction.ldrh(cond, rt, .sp, .{ .offset = offset })),
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.ldrsb_stack_argument => try emit.writeInstruction(Instruction.ldrsb(cond, rt, .sp, .{ .offset = offset })),
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.ldrsh_stack_argument => try emit.writeInstruction(Instruction.ldrsh(cond, rt, .sp, .{ .offset = offset })),
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else => unreachable,
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};
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const ldr_workaround = switch (builtin.zig_backend) {
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.stage1 => ldr.*,
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else => ldr,
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};
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try emit.writeInstruction(ldr_workaround(
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cond,
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r_stack_offset.rt,
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.fp,
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.{ .offset = offset },
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));
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}
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},
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else => unreachable,
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}
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