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https://github.com/ziglang/zig.git
synced 2026-02-03 21:23:36 +00:00
stage2 ARM: rework cmp in preparation for switch
This commit is contained in:
joachimschmidt557
parent
e498fb1550
commit
4fdacca512
@ -813,6 +813,17 @@ fn finishAir(self: *Self, inst: Air.Inst.Index, result: MCValue, operands: [Live
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self.register_manager.getRegAssumeFree(reg, inst);
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}
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},
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.register_c_flag,
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.register_v_flag,
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=> |reg| {
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if (self.register_manager.isRegFree(reg)) {
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self.register_manager.getRegAssumeFree(reg, inst);
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}
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self.cpsr_flags_inst = inst;
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},
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.cpsr_flags => {
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self.cpsr_flags_inst = inst;
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},
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else => {},
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}
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}
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@ -2462,56 +2473,28 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
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const reg_lock = self.register_manager.lockRegAssumeUnused(reg);
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defer self.register_manager.unlockReg(reg_lock);
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switch (index) {
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0 => {
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// get wrapped value: return register
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break :result MCValue{ .register = reg };
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},
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1 => {
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// get overflow bit: return C or V flag
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if (self.liveness.operandDies(inst, 0)) {
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self.cpsr_flags_inst = inst;
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const field: MCValue = switch (index) {
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// get wrapped value: return register
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0 => MCValue{ .register = reg },
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const cond: Condition = switch (mcv) {
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.register_c_flag => .cs,
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.register_v_flag => .vs,
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else => unreachable,
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};
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// get overflow bit: return C or V flag
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1 => MCValue{ .cpsr_flags = switch (mcv) {
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.register_c_flag => .cs,
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.register_v_flag => .vs,
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else => unreachable,
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} },
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break :result MCValue{ .cpsr_flags = cond };
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} else {
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const dest_reg = try self.register_manager.allocReg(null, gp);
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// mov reg, #0
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_ = try self.addInst(.{
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.tag = .mov,
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.data = .{ .rr_op = .{
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.rd = dest_reg,
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.rn = .r0,
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.op = Instruction.Operand.fromU32(0).?,
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} },
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});
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// C flag: movcs reg, #1
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// V flag: movvs reg, #1
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_ = try self.addInst(.{
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.tag = .mov,
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.cond = switch (mcv) {
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.register_c_flag => .cs,
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.register_v_flag => .vs,
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else => unreachable,
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},
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.data = .{ .rr_op = .{
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.rd = dest_reg,
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.rn = .r0,
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.op = Instruction.Operand.fromU32(1).?,
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} },
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});
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break :result MCValue{ .register = dest_reg };
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}
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},
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else => unreachable,
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};
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if (self.liveness.operandDies(inst, 0)) {
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break :result field;
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} else {
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// Copy to new register
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const dest_reg = try self.register_manager.allocReg(null, gp);
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try self.genSetReg(struct_ty.structFieldType(index), dest_reg, field);
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break :result MCValue{ .register = dest_reg };
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}
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},
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else => return self.fail("TODO implement codegen struct_field_val for {}", .{mcv}),
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@ -3570,55 +3553,91 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {
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fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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var int_buffer: Type.Payload.Bits = undefined;
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const int_ty = switch (lhs_ty.zigTypeTag()) {
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.Optional => blk: {
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var opt_buffer: Type.Payload.ElemType = undefined;
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const payload_ty = lhs_ty.optionalChild(&opt_buffer);
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if (!payload_ty.hasRuntimeBitsIgnoreComptime()) {
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break :blk Type.initTag(.u1);
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} else if (lhs_ty.isPtrLikeOptional()) {
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break :blk Type.usize;
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} else {
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return self.fail("TODO ARM cmp non-pointer optionals", .{});
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}
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},
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.Float => return self.fail("TODO ARM cmp floats", .{}),
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.Enum => lhs_ty.intTagType(&int_buffer),
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.Int => lhs_ty,
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.Bool => Type.initTag(.u1),
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.Pointer => Type.usize,
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.ErrorSet => Type.initTag(.u16),
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else => unreachable,
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};
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const int_info = int_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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try self.spillCompareFlagsIfOccupied();
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self.cpsr_flags_inst = inst;
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_ = try self.binOp(.cmp_eq, lhs, rhs, int_ty, int_ty, BinOpMetadata{
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.lhs = bin_op.lhs,
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.rhs = bin_op.rhs,
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.inst = inst,
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});
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break :result switch (int_info.signedness) {
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.signed => MCValue{ .cpsr_flags = Condition.fromCompareOperatorSigned(op) },
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.unsigned => MCValue{ .cpsr_flags = Condition.fromCompareOperatorUnsigned(op) },
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};
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} else {
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return self.fail("TODO ARM cmp for ints > 32 bits", .{});
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}
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else blk: {
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const operands: BinOpOperands = .{ .inst = .{
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.inst = inst,
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.lhs = bin_op.lhs,
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.rhs = bin_op.rhs,
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} };
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break :blk try self.cmp(operands, lhs_ty, op);
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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const BinOpOperands = union(enum) {
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inst: struct {
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inst: Air.Inst.Index,
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lhs: Air.Inst.Ref,
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rhs: Air.Inst.Ref,
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},
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mcv: struct {
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lhs: MCValue,
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rhs: MCValue,
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},
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};
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fn cmp(
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self: *Self,
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operands: BinOpOperands,
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lhs_ty: Type,
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op: math.CompareOperator,
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) !MCValue {
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var int_buffer: Type.Payload.Bits = undefined;
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const int_ty = switch (lhs_ty.zigTypeTag()) {
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.Optional => blk: {
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var opt_buffer: Type.Payload.ElemType = undefined;
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const payload_ty = lhs_ty.optionalChild(&opt_buffer);
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if (!payload_ty.hasRuntimeBitsIgnoreComptime()) {
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break :blk Type.initTag(.u1);
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} else if (lhs_ty.isPtrLikeOptional()) {
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break :blk Type.usize;
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} else {
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return self.fail("TODO ARM cmp non-pointer optionals", .{});
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}
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},
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.Float => return self.fail("TODO ARM cmp floats", .{}),
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.Enum => lhs_ty.intTagType(&int_buffer),
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.Int => lhs_ty,
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.Bool => Type.initTag(.u1),
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.Pointer => Type.usize,
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.ErrorSet => Type.initTag(.u16),
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else => unreachable,
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};
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const int_info = int_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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try self.spillCompareFlagsIfOccupied();
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switch (operands) {
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.inst => |inst_op| {
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const metadata: BinOpMetadata = .{
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.inst = inst_op.inst,
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.lhs = inst_op.lhs,
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.rhs = inst_op.rhs,
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};
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const lhs = try self.resolveInst(inst_op.lhs);
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const rhs = try self.resolveInst(inst_op.rhs);
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self.cpsr_flags_inst = inst_op.inst;
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_ = try self.binOp(.cmp_eq, lhs, rhs, int_ty, int_ty, metadata);
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},
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.mcv => |mcv_op| {
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_ = try self.binOp(.cmp_eq, mcv_op.lhs, mcv_op.rhs, int_ty, int_ty, null);
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},
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}
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return switch (int_info.signedness) {
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.signed => MCValue{ .cpsr_flags = Condition.fromCompareOperatorSigned(op) },
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.unsigned => MCValue{ .cpsr_flags = Condition.fromCompareOperatorUnsigned(op) },
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};
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} else {
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return self.fail("TODO ARM cmp for ints > 32 bits", .{});
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}
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}
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fn airCmpVector(self: *Self, inst: Air.Inst.Index) !void {
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_ = inst;
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return self.fail("TODO implement airCmpVector for {}", .{self.target.cpu.arch});
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@ -4081,10 +4100,137 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {
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fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
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const pl_op = self.air.instructions.items(.data)[inst].pl_op;
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const condition = pl_op.operand;
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_ = condition;
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return self.fail("TODO airSwitch for {}", .{self.target.cpu.arch});
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// return self.finishAir(inst, .dead, .{ condition, .none, .none });
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const condition_ty = self.air.typeOf(pl_op.operand);
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const switch_br = self.air.extraData(Air.SwitchBr, pl_op.payload);
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const liveness = try self.liveness.getSwitchBr(
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self.gpa,
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inst,
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switch_br.data.cases_len + 1,
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);
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defer self.gpa.free(liveness.deaths);
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// If the condition dies here in this switch instruction, process
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// that death now instead of later as this has an effect on
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// whether it needs to be spilled in the branches
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if (self.liveness.operandDies(inst, 0)) {
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const op_int = @enumToInt(pl_op.operand);
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if (op_int >= Air.Inst.Ref.typed_value_map.len) {
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const op_index = @intCast(Air.Inst.Index, op_int - Air.Inst.Ref.typed_value_map.len);
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self.processDeath(op_index);
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}
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}
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var extra_index: usize = switch_br.end;
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var case_i: u32 = 0;
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while (case_i < switch_br.data.cases_len) : (case_i += 1) {
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const case = self.air.extraData(Air.SwitchBr.Case, extra_index);
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const items = @bitCast([]const Air.Inst.Ref, self.air.extra[case.end..][0..case.data.items_len]);
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assert(items.len > 0);
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const case_body = self.air.extra[case.end + items.len ..][0..case.data.body_len];
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extra_index = case.end + items.len + case_body.len;
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var relocs = try self.gpa.alloc(u32, items.len);
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defer self.gpa.free(relocs);
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if (items.len == 1) {
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const condition = try self.resolveInst(pl_op.operand);
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const item = try self.resolveInst(items[0]);
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const operands: BinOpOperands = .{ .mcv = .{
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.lhs = condition,
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.rhs = item,
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} };
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const cmp_result = try self.cmp(operands, condition_ty, .neq);
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relocs[0] = try self.addInst(.{
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.tag = .b,
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.cond = cmp_result.cpsr_flags,
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.data = .{ .inst = undefined }, // populated later through performReloc
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});
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} else {
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return self.fail("TODO switch with multiple items", .{});
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}
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// Capture the state of register and stack allocation state so that we can revert to it.
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const parent_next_stack_offset = self.next_stack_offset;
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const parent_free_registers = self.register_manager.free_registers;
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const parent_cpsr_flags_inst = self.cpsr_flags_inst;
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var parent_stack = try self.stack.clone(self.gpa);
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defer parent_stack.deinit(self.gpa);
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const parent_registers = self.register_manager.registers;
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try self.branch_stack.append(.{});
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errdefer {
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_ = self.branch_stack.pop();
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}
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try self.ensureProcessDeathCapacity(liveness.deaths[case_i].len);
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for (liveness.deaths[case_i]) |operand| {
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self.processDeath(operand);
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}
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try self.genBody(case_body);
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// Revert to the previous register and stack allocation state.
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var saved_case_branch = self.branch_stack.pop();
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defer saved_case_branch.deinit(self.gpa);
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self.register_manager.registers = parent_registers;
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self.cpsr_flags_inst = parent_cpsr_flags_inst;
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self.stack.deinit(self.gpa);
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self.stack = parent_stack;
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parent_stack = .{};
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self.next_stack_offset = parent_next_stack_offset;
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self.register_manager.free_registers = parent_free_registers;
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for (relocs) |reloc| {
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try self.performReloc(reloc);
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}
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}
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if (switch_br.data.else_body_len > 0) {
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const else_body = self.air.extra[extra_index..][0..switch_br.data.else_body_len];
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// Capture the state of register and stack allocation state so that we can revert to it.
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const parent_next_stack_offset = self.next_stack_offset;
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const parent_free_registers = self.register_manager.free_registers;
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const parent_cpsr_flags_inst = self.cpsr_flags_inst;
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var parent_stack = try self.stack.clone(self.gpa);
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defer parent_stack.deinit(self.gpa);
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const parent_registers = self.register_manager.registers;
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try self.branch_stack.append(.{});
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errdefer {
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_ = self.branch_stack.pop();
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}
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const else_deaths = liveness.deaths.len - 1;
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try self.ensureProcessDeathCapacity(liveness.deaths[else_deaths].len);
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for (liveness.deaths[else_deaths]) |operand| {
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self.processDeath(operand);
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}
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try self.genBody(else_body);
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// Revert to the previous register and stack allocation state.
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var saved_case_branch = self.branch_stack.pop();
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defer saved_case_branch.deinit(self.gpa);
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self.register_manager.registers = parent_registers;
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self.cpsr_flags_inst = parent_cpsr_flags_inst;
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self.stack.deinit(self.gpa);
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self.stack = parent_stack;
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parent_stack = .{};
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self.next_stack_offset = parent_next_stack_offset;
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self.register_manager.free_registers = parent_free_registers;
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// TODO consolidate returned MCValues between prongs and else branch like we do
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// in airCondBr.
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}
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// We already took care of pl_op.operand earlier, so we're going
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// to pass .none here
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return self.finishAir(inst, .unreach, .{ .none, .none, .none });
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}
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fn performReloc(self: *Self, inst: Mir.Inst.Index) !void {
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