Andrew Kelley
aeaef8c0ff
update std lib and compiler sources to new for loop syntax
2023-02-18 19:17:21 -07:00
Jakub Konka
5de2aae63c
link: decouple DI atoms from linker atoms, and manage them in Dwarf linker
2023-02-01 15:03:55 +01:00
Jakub Konka
b3277c8936
link: make Plan9 atoms fully owned by the linker
2023-02-01 11:12:53 +01:00
Jakub Konka
4404c4d200
link: make Elf atoms fully owned by the linker
2023-01-31 17:54:12 +01:00
Jakub Konka
e1b9800ffa
elf: migrate to new non-allocateDeclIndexes API
2023-01-26 14:29:14 +01:00
Jakub Konka
a95d58caf2
self-hosted: rename codegen Result.appended to Result.ok
2023-01-25 10:28:18 +01:00
Jakub Konka
4983da40d0
self-hosted: remove unused externally_managed prong for Decls code
2023-01-25 10:10:50 +01:00
joachimschmidt557
c0284e242f
stage2 ARM: add basic debug info for locals
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Also disables one behavior test which was failing
2023-01-22 12:00:04 +01:00
Veikka Tuominen
4e64373fc0
fix generic function arg debug info referencing wrong parameter
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Closes #14123
2022-12-30 17:00:50 +02:00
Andrew Kelley
aca9c74e80
Merge pull request #13914 from Vexu/variadic
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implement defining C variadic functions
2022-12-18 16:24:13 -05:00
r00ster91
aac2d6b56f
std.builtin: rename Type.UnionField and Type.StructField's field_type to type
2022-12-17 14:11:33 +01:00
Veikka Tuominen
9bb1104e37
implement defining C variadic functions
2022-12-17 13:22:09 +02:00
Veikka Tuominen
8a0a6b7387
port packed vector elem ptr logic from stage1
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Closes #12812
Closes #13925
2022-12-15 21:06:35 -05:00
Veikka Tuominen
7b2a936173
remove stack option from @call
2022-12-13 12:52:21 +02:00
Veikka Tuominen
9d93b2ccf1
Eliminate BoundFn type from the language
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Closes #9484
2022-12-09 20:37:18 -07:00
Andrew Kelley
fdbb0fb7b9
Merge pull request #13744 from Vexu/stage2-fixes
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Improve error messages, fix dependency loops
2022-12-03 00:42:11 -05:00
Veikka Tuominen
0e38cc16d5
Sema: fix comparisons between lazy and runtime values
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Closes #12498
2022-12-03 00:09:23 +02:00
Jakub Konka
bfd36cbf97
dwarf: pass linker Tag and owner Decl.Index instead of *Atom
2022-12-02 13:17:52 +01:00
Jakub Konka
3ec0520bac
dwarf: use common DI union object for arg and var gen
2022-12-02 12:22:17 +01:00
Jakub Konka
17ab40f755
dwarf: refactor arm and riscv64 to the new scheme
2022-12-01 20:06:11 +01:00
Jakub Konka
7d0af639d8
dwarf: update arm and riscv codegens to the new model
2022-12-01 14:32:09 +01:00
Andrew Kelley
ceb0a632cf
std.mem.Allocator: allow shrink to fail
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closes #13535
2022-11-29 23:30:38 -07:00
joachimschmidt557
89c374cd2d
stage2 ARM: misc fixes
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- remove redundant `new` from `binOpRegisterNew` name
- fix mul_with_overflow
2022-11-21 08:23:07 +01:00
Veikka Tuominen
d03c47bf85
Sema: use runtime_value instead of creating allocs
2022-10-27 21:08:25 -04:00
Cody Tapscott
724d753638
stage2: Add .save_err_return_trace_index AIR op
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This is encoded as a primitive AIR instruction to resolve one corner
case: A function may include a `catch { ... }` or `else |err| { ... }`
block but not call any errorable fn. In that case, there is no error
return trace to save the index of and codegen needs to avoid
interacting with the non-existing error trace.
By using a primitive AIR op, we can depend on Liveness to mark this
unused in this corner case.
2022-10-21 10:44:20 -07:00
Ali Chraghi
ca27055cda
all: rename @maximum to @max and @minimum to @min
2022-10-18 14:15:16 +03:00
Robin Voetter
5d429b03e3
stage2: add @addrSpaceCast builtin
2022-10-12 20:36:12 +02:00
joachimschmidt557
f014de6456
stage2 ARM: fix debug info for arguments passed in registers
2022-09-20 17:14:31 +02:00
joachimschmidt557
258b058eec
stage2 ARM: make sub_sp_scratch MIR instruction use r4
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r0 is used for argument passing, so this register is not available as
a scratch register upon function entry.
2022-09-20 17:14:27 +02:00
Andrew Kelley
bec70a1a39
stage2: remove pointless discards from source code
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Good riddance!
2022-09-13 02:04:20 -07:00
joachimschmidt557
94499898e5
stage2 ARM: implement basic array_elem_val
2022-09-09 20:26:04 +02:00
joachimschmidt557
b976997e16
stage2 ARM: implement ptr_elem_val
2022-09-09 19:17:18 +02:00
joachimschmidt557
a0a7d15142
stage2 ARM: support larger function stacks
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This is done by introducing a new Mir pseudo-instruction
2022-09-09 19:17:18 +02:00
joachimschmidt557
3794f2c493
stage2 ARM: implement struct_field_val for registers
2022-09-09 19:17:18 +02:00
joachimschmidt557
25729d6155
stage2 ARM: fix multiple uses of reuseOperand
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- add missing checks whether destination fits into the operand
- remove reuseOperand invocations from airIsNullPtr and similar
functions as we need to load the operands into temporary locations
2022-09-09 19:17:18 +02:00
joachimschmidt557
261fec8036
stage2 ARM: amend implementation of various AIR instructions
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- unwrap_errunion_err for registers
- unwrap_errunion_payload for registers
- ptr_slice_len_ptr for all MCValues
- ptr_slice_ptr_ptr for all MCValues
2022-09-09 19:17:17 +02:00
joachimschmidt557
e2b029e2c8
stage2 ARM: implement field_parent_ptr
2022-09-09 19:17:17 +02:00
joachimschmidt557
481bd4761a
stage2 ARM: remove remaining uses of binOp{Register,Immediate}
2022-09-09 19:17:17 +02:00
joachimschmidt557
95b8a5f157
stage2 ARM: extract remaining operations out of binOp
2022-09-09 19:17:17 +02:00
joachimschmidt557
fdb2c80bdc
stage2 ARM: extract mul, div, and mod out of binOp
2022-09-09 19:17:17 +02:00
joachimschmidt557
ed4be06883
stage2 ARM: extract add+sub from binOp
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This commit also lays the groundwork for further extractions from
binOp.
2022-09-09 19:17:17 +02:00
joachimschmidt557
86dd123392
stage2 ARM: move cmp to new allocReg mechanism; remove from binOp
2022-09-09 19:17:17 +02:00
joachimschmidt557
0414ef591a
stage2 ARM: introduce allocRegs
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This new register allocation mechanism which is designed to be more
generic and flexible will replace binOp.
2022-09-09 19:17:16 +02:00
joachimschmidt557
28cc363947
stage2 ARM: improve Mir representation of mov and cmp
2022-09-09 19:17:13 +02:00
Jakub Konka
601f2147e0
coff: cleanup relocations; remove COFF support from other backends
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Given that COFF will want to support PIC from ground-up, there is no
point in leaving outdated code for COFF in other backends such as
arm or aarch64. Instead, when we are ready to look into those, we
can start figuring out what to add and where.
2022-08-30 10:42:21 +02:00
Jakub Konka
90b3599c68
coff: reorganize the linker
2022-08-30 10:42:21 +02:00
Veikka Tuominen
40eac90280
Merge pull request #12416 from Vexu/stage2-safety
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Stage2 error set safety improvements
2022-08-15 11:32:26 +03:00
joachimschmidt557
c9d9fd53a6
stage2 ARM: add inline memcpy to genSetStack
2022-08-13 17:00:03 +02:00
joachimschmidt557
91969ad908
stage2 ARM: Fix tracking of function return values
2022-08-13 17:00:03 +02:00
joachimschmidt557
4c5156544b
stage2 ARM: pass stack arguments in opposite order
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Earlier arguments have a smaller address (i.e. towards the bottom of
the stack)
2022-08-13 17:00:00 +02:00
