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https://github.com/ziglang/zig.git
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stage2 ARM: misc fixes
- remove redundant `new` from `binOpRegisterNew` name - fix mul_with_overflow
This commit is contained in:
joachimschmidt557
Joachim Schmidt
parent
c45c6cd492
commit
89c374cd2d
@ -1416,8 +1416,9 @@ fn airBinOp(self: *Self, inst: Air.Inst.Index, tag: Air.Inst.Tag) !void {
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.div_float => try self.divFloat(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.div_trunc => try self.div(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.div_floor => try self.div(tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.div_trunc => try self.divTrunc(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.div_floor => try self.divFloor(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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.div_exact => try self.divExact(lhs_bind, rhs_bind, lhs_ty, rhs_ty, inst),
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@ -1567,12 +1568,12 @@ fn airOverflow(self: *Self, inst: Air.Inst.Index) !void {
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const dest = blk: {
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if (rhs_immediate_ok) {
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break :blk try self.binOpImmediateNew(mir_tag, lhs_bind, rhs_immediate.?, lhs_ty, false, null);
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break :blk try self.binOpImmediate(mir_tag, lhs_bind, rhs_immediate.?, lhs_ty, false, null);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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break :blk try self.binOpImmediateNew(mir_tag, rhs_bind, lhs_immediate.?, rhs_ty, true, null);
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break :blk try self.binOpImmediate(mir_tag, rhs_bind, lhs_immediate.?, rhs_ty, true, null);
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} else {
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break :blk try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, null);
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break :blk try self.binOpRegister(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, null);
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}
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};
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@ -1625,7 +1626,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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.unsigned => .mul,
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};
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const dest = try self.binOpRegisterNew(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, null);
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const dest = try self.binOpRegister(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, null);
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const dest_reg = dest.register;
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const dest_reg_lock = self.register_manager.lockRegAssumeUnused(dest_reg);
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defer self.register_manager.unlockReg(dest_reg_lock);
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@ -3123,7 +3124,7 @@ fn allocRegs(
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/// instructions which are binary operations acting on two registers
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///
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/// Returns the destination register
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fn binOpRegisterNew(
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fn binOpRegister(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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@ -3196,7 +3197,7 @@ fn binOpRegisterNew(
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/// an immediate
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///
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/// Returns the destination register
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fn binOpImmediateNew(
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fn binOpImmediate(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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@ -3265,11 +3266,11 @@ fn addSub(
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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const mod = self.bin_file.options.module.?;
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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@ -3298,12 +3299,12 @@ fn addSub(
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediateNew(mir_tag, lhs_bind, rhs_immediate.?, lhs_ty, false, maybe_inst);
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return try self.binOpImmediate(mir_tag, lhs_bind, rhs_immediate.?, lhs_ty, false, maybe_inst);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediateNew(mir_tag, rhs_bind, lhs_immediate.?, rhs_ty, true, maybe_inst);
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return try self.binOpImmediate(mir_tag, rhs_bind, lhs_immediate.?, rhs_ty, true, maybe_inst);
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} else {
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return try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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return try self.binOpRegister(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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@ -3321,18 +3322,18 @@ fn mul(
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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const mod = self.bin_file.options.module.?;
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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// TODO add optimisations for multiplication
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// with immediates, for example a * 2 can be
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// lowered to a << 1
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return try self.binOpRegisterNew(.mul, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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return try self.binOpRegister(.mul, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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@ -3361,22 +3362,19 @@ fn divFloat(
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}
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}
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fn div(
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fn divTrunc(
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self: *Self,
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tag: Air.Inst.Tag,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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_ = tag;
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const mod = self.bin_file.options.module.?;
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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@ -3390,7 +3388,50 @@ fn div(
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if (rhs_immediate) |imm| {
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if (std.math.isPowerOfTwo(imm)) {
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const shift = std.math.log2_int(u32, imm);
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return try self.binOpImmediateNew(.lsr, lhs_bind, shift, lhs_ty, false, maybe_inst);
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return try self.binOpImmediate(.lsr, lhs_bind, shift, lhs_ty, false, maybe_inst);
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} else {
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return self.fail("TODO ARM integer division by constants", .{});
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}
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} else {
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return self.fail("TODO ARM integer division", .{});
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}
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},
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}
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} else {
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return self.fail("TODO ARM integer division for integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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}
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fn divFloor(
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self: *Self,
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lhs_bind: ReadArg.Bind,
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rhs_bind: ReadArg.Bind,
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lhs_ty: Type,
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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const mod = self.bin_file.options.module.?;
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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switch (int_info.signedness) {
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.signed => {
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return self.fail("TODO ARM signed integer division", .{});
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},
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.unsigned => {
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const rhs_immediate = try rhs_bind.resolveToImmediate(self);
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if (rhs_immediate) |imm| {
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if (std.math.isPowerOfTwo(imm)) {
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const shift = std.math.log2_int(u32, imm);
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return try self.binOpImmediate(.lsr, lhs_bind, shift, lhs_ty, false, maybe_inst);
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} else {
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return self.fail("TODO ARM integer division by constants", .{});
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}
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@ -3436,11 +3477,11 @@ fn rem(
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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const mod = self.bin_file.options.module.?;
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const mod = self.bin_file.options.module.?;
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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@ -3522,28 +3563,26 @@ fn wrappingArithmetic(
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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const base_tag: Air.Inst.Tag = switch (tag) {
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.addwrap => .add,
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.subwrap => .sub,
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.mulwrap => .mul,
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else => unreachable,
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};
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// Generate an add/sub/mul
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const result = try self.addSub(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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// Truncate if necessary
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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const result_reg = result.register;
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// Generate an add/sub/mul
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const result: MCValue = switch (tag) {
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.addwrap => try self.addSub(.add, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst),
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.subwrap => try self.addSub(.sub, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst),
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.mulwrap => try self.mul(lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst),
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else => unreachable,
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};
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// Truncate if necessary
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const result_reg = result.register;
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if (int_info.bits < 32) {
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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return result;
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} else return result;
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}
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return result;
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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@ -3582,12 +3621,12 @@ fn bitwise(
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediateNew(mir_tag, lhs_bind, rhs_immediate.?, lhs_ty, false, maybe_inst);
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return try self.binOpImmediate(mir_tag, lhs_bind, rhs_immediate.?, lhs_ty, false, maybe_inst);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediateNew(mir_tag, rhs_bind, lhs_immediate.?, rhs_ty, true, maybe_inst);
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return try self.binOpImmediate(mir_tag, rhs_bind, lhs_immediate.?, rhs_ty, true, maybe_inst);
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} else {
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return try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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return try self.binOpRegister(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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@ -3623,9 +3662,9 @@ fn shiftExact(
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};
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if (rhs_immediate) |imm| {
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return try self.binOpImmediateNew(mir_tag, lhs_bind, imm, lhs_ty, false, maybe_inst);
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return try self.binOpImmediate(mir_tag, lhs_bind, imm, lhs_ty, false, maybe_inst);
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} else {
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return try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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return try self.binOpRegister(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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}
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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@ -3644,34 +3683,34 @@ fn shiftNormal(
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rhs_ty: Type,
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maybe_inst: ?Air.Inst.Index,
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) InnerError!MCValue {
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const base_tag: Air.Inst.Tag = switch (tag) {
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.shl => .shl_exact,
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.shr => .shr_exact,
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else => unreachable,
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};
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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// Generate a shl_exact/shr_exact
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const result: MCValue = switch (tag) {
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.shl => try self.shiftExact(.shl_exact, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst),
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.shr => try self.shiftExact(.shr_exact, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst),
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else => unreachable,
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};
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// Generate a shl_exact/shr_exact
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const result = try self.shiftExact(base_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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// Truncate if necessary
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switch (tag) {
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.shr => return result,
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.shl => {
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const result_reg = result.register;
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if (int_info.bits < 32) {
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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}
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// Truncate if necessary
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switch (tag) {
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.shr => return result,
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.shl => switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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const result_reg = result.register;
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if (int_info.bits < 32) {
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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return result;
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} else return result;
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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},
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else => unreachable,
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}
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},
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else => unreachable,
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} else {
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return self.fail("TODO ARM binary operations on integers > u32/i32", .{});
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}
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},
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else => unreachable,
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}
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@ -3698,12 +3737,12 @@ fn booleanOp(
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};
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if (rhs_immediate) |imm| {
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return try self.binOpImmediateNew(mir_tag, lhs_bind, imm, lhs_ty, false, maybe_inst);
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return try self.binOpImmediate(mir_tag, lhs_bind, imm, lhs_ty, false, maybe_inst);
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} else if (lhs_immediate) |imm| {
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// swap lhs and rhs
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return try self.binOpImmediateNew(mir_tag, rhs_bind, imm, rhs_ty, true, maybe_inst);
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return try self.binOpImmediate(mir_tag, rhs_bind, imm, rhs_ty, true, maybe_inst);
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} else {
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return try self.binOpRegisterNew(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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return try self.binOpRegister(mir_tag, lhs_bind, rhs_bind, lhs_ty, rhs_ty, maybe_inst);
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}
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},
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else => unreachable,
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