Veikka Tuominen
eee8fffec7
stage2: implement error return traces
2022-05-16 17:42:51 -07:00
Andrew Kelley
5888446c03
Merge pull request #11316 from wsengir/stage2-overflow-safety
...
stage2: vectorized overflow arithmetic, integer overflow safety, left-shift overflow safety
2022-05-16 20:40:57 -04:00
Thiago Teodoro Pereira Silva
7a4758ed78
std.os: add timerfd_create, timerfd_settime and timerfd_gettime
2022-05-17 00:56:33 +02:00
leesongun
1de7b8d26c
std.math.powi: use standard definition of underflow/overflow, implement u0, i0, i1 edge case (#11499 )
2022-05-16 18:28:20 -04:00
Isaac Freund
1392c24166
std.os: Add memfd_create for FreeBSD
...
This is minorly breaking as e.g. std.os.linux.MFD_CLOEXEC is now
std.os.linux.MFD.CLOEXEC.
2022-05-16 17:43:44 -04:00
Andrew Kelley
f33b3fc3ea
zig.h: add casts for overflow arithmetic operations
...
This avoids the following error:
```
error: incompatible pointer types passing 'int64_t *' (aka 'long long *') to parameter of type 'long *'
overflow = __builtin_saddl_overflow(lhs, rhs, res);
^~~
```
My previous understanding was that this error would not occur because
prior to this line we check that int64_t is equivalent to long, like
this:
```c
```
However, it appears that this is still a warning in C if int64_t is
primarily aliased to `long long`, even though `long` and `long long` are
the same thing.
2022-05-16 14:30:28 -07:00
Jakub Konka
a0de0adb8e
arm: disable recursive fibonacci
2022-05-16 13:55:26 -07:00
Jakub Konka
7f96ca101a
arm: sub_with_overflow should always track V flag
2022-05-16 13:55:26 -07:00
Jakub Konka
852c820841
aarch64: sub_with_overflow should always track V flag
2022-05-16 13:55:26 -07:00
Andrew Kelley
a84be7e988
zig.h: improve overflow shl
...
* zig_addo_u128: fix type-o
* redo the shift-left overflow inline functions. no need to depend on
compiler-rt.
2022-05-16 13:55:26 -07:00
Luuk de Gram
160aa4c11d
wasm: Improve shl_with_overflow
...
This re-implements the shl_with_overflow operation from scratch,
making it a lot more robust and outputs the equal code to the LLVM backend.
2022-05-16 13:55:26 -07:00
Luuk de Gram
0a2d3d4155
wasm: Improve overflow add/sub for ints <= 64bits
...
The implementation for add_with_overflow and sub_with_overflow is now a lot
more robust and takes account for signed integers and arbitrary integer bitsizes.
The final output is equal to that of the LLVM backend.
2022-05-16 13:55:26 -07:00
Jakub Konka
b94d165b69
x64: fix capacity prealloc limit in lowerToMrEnc helper
2022-05-16 13:55:26 -07:00
Andrew Kelley
316bf4fce5
disable 5 failing stage2_wasm tests
2022-05-16 13:55:26 -07:00
Andrew Kelley
03ed0f0d28
C backend: implement overflow arithmetic
...
Most of the work here was additions to zig.h. The lowering code is
mainly responsible for calling the correct function name depending on
the operand type.
Some of the compiler-rt calls here are not implemented yet and are
non-standard symbols due to the C programming language not needing them.
After this commit, the behavior tests with -ofmt=c are passing again.
2022-05-16 13:55:26 -07:00
William Sengir
a5ea22d069
LLVM: correctly pad result tuple of airOverflow
2022-05-16 13:55:26 -07:00
William Sengir
bb3532e775
stage2: add more vector overflow tests
2022-05-16 13:55:26 -07:00
William Sengir
21be3d9166
stage2: add vectorized overflow arithmetic behavior tests
2022-05-16 13:55:26 -07:00
William Sengir
afc714d5e5
stage2: implement runtime safety checks for shl_exact
2022-05-16 13:55:26 -07:00
William Sengir
c2980f332e
Sema: implement integer overflow safety for add, sub, mul
2022-05-16 13:55:26 -07:00
William Sengir
eb06c78a8a
Sema: vectorize overflow arithmetic
2022-05-16 13:55:26 -07:00
William Sengir
86a928ce61
stage2: perform comptime vectorization of *_with_overflow in Value
2022-05-16 13:55:26 -07:00
William Sengir
e8117bab6f
stage2: clean up creation of boolean Values
2022-05-16 13:55:26 -07:00
William Sengir
6b5c87957b
stage2: handle vectors in Value.intFitsInType
2022-05-16 13:55:26 -07:00
William Sengir
ca1ab38d3a
stage2: add global Type constant for u1
2022-05-16 13:55:26 -07:00
William Sengir
c2cb9b7cad
stage2: vectorize shl_with_overflow in LLVM backend
2022-05-16 13:55:26 -07:00
William Sengir
c641fb8f05
stage2: fix {add,sub,mul}_with_overflow vectorization in LLVM backend
2022-05-16 13:55:26 -07:00
Koakuma
b618dbdf69
stage2: sparc64: Implement SPARCv9 mulx
2022-05-16 23:30:54 +07:00
Koakuma
7245aad689
stage2: sparc64: Implement airBinOp for addition
2022-05-16 23:30:54 +07:00
Koakuma
67a1fedf84
stage2: sparc64: Implement airUnwrapErrErr
2022-05-16 23:30:54 +07:00
Koakuma
77eef33c04
stage2: sparc64: Implement airStructFieldPtrIndex
2022-05-16 23:30:54 +07:00
Koakuma
26116211ec
stage2: sparc64: Implement inline memcpy for genSetStack
2022-05-16 23:30:54 +07:00
Koakuma
7822426ff2
stage2: sparc64: Implement airSliceElemVal
2022-05-16 23:30:54 +07:00
Koakuma
ccf438e4de
stage2: sparc64: Replace freezeRegs with RegisterLock
2022-05-16 23:30:54 +07:00
Koakuma
26e3d36d74
stage2: sparc64: Implement airSliceLen
2022-05-16 23:30:54 +07:00
Koakuma
8ea80fdf7a
stage2: sparc64: Implement airLoop
2022-05-16 23:30:47 +07:00
Koakuma
e4a725c597
stage2: sparc64: Implement airBitCast
2022-05-16 23:17:11 +07:00
Koakuma
0c8ce9ed9d
stage2: sparc64: Implement airCmp
2022-05-16 23:17:11 +07:00
Koakuma
ae2d6b7eea
stage2: sparc64: Add BPr support for airCondBr
2022-05-16 23:17:11 +07:00
Koakuma
e057ff2496
stage2: sparc64: Implement SPARCv9 bpr
2022-05-16 23:17:11 +07:00
Koakuma
8f8853cd4f
stage2: sparc64: Implement airLoad/airStore
2022-05-16 23:17:06 +07:00
Koakuma
0b54649cac
stage2: sparc64: Implement error value generation
2022-05-16 22:48:49 +07:00
Koakuma
3ab6634370
stage2: sparc64: Implement airAlloc
2022-05-16 22:48:49 +07:00
Koakuma
339b0517b3
stage2: sparc64: Implement SPARCv9 bpcc
2022-05-16 22:48:49 +07:00
Koakuma
5d260eb573
stage2: sparc64: Implement SPARCv9 subcc
2022-05-16 22:47:53 +07:00
Koakuma
2770f9a034
stage2: sparc64: Implement airBr
2022-05-16 22:47:53 +07:00
Koakuma
b6de8d2565
stage2: sparc64: Implement airUnwrapErrPayload
2022-05-16 22:47:53 +07:00
Koakuma
2dc2ab091e
stage2: sparc64: Implement airCondBr from flags register
2022-05-16 22:47:53 +07:00
Koakuma
fd781195de
stage2: sparc64: Split the conditionals between integer and FP ones
...
On SPARCv9 the integer and FP conditional branch codes doesn't align
with each other at all, so the two need to be treated separately.
2022-05-16 22:47:52 +07:00
Koakuma
662a61fcc3
stage2: sparc64: Implement airIsErr and airIsNonErr
2022-05-16 22:47:52 +07:00
