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stage2: sparc64: Implement airSliceElemVal
This commit is contained in:
Koakuma
parent
ccf438e4de
commit
7822426ff2
@ -30,6 +30,7 @@ const build_options = @import("build_options");
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const bits = @import("bits.zig");
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const abi = @import("abi.zig");
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const Instruction = bits.Instruction;
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const ShiftWidth = Instruction.ShiftWidth;
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const Register = bits.Register;
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const Self = @This();
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@ -637,7 +638,7 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.ptr_slice_ptr_ptr => @panic("TODO try self.airPtrSlicePtrPtr(inst)"),
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.array_elem_val => @panic("TODO try self.airArrayElemVal(inst)"),
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.slice_elem_val => @panic("TODO try self.airSliceElemVal(inst)"),
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.slice_elem_val => try self.airSliceElemVal(inst),
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.slice_elem_ptr => @panic("TODO try self.airSliceElemPtr(inst)"),
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.ptr_elem_val => @panic("TODO try self.airPtrElemVal(inst)"),
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.ptr_elem_ptr => @panic("TODO try self.airPtrElemPtr(inst)"),
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@ -1374,16 +1375,48 @@ fn airRetPtr(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, .{ .ptr_stack_offset = stack_offset }, .{ .none, .none, .none });
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}
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fn airStore(self: *Self, inst: Air.Inst.Index) !void {
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fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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const is_volatile = false; // TODO
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const ptr = try self.resolveInst(bin_op.lhs);
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const value = try self.resolveInst(bin_op.rhs);
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const ptr_ty = self.air.typeOf(bin_op.lhs);
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const value_ty = self.air.typeOf(bin_op.rhs);
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try self.store(ptr, value, ptr_ty, value_ty);
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if (!is_volatile and self.liveness.isUnused(inst)) return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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const result: MCValue = result: {
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const slice_mcv = try self.resolveInst(bin_op.lhs);
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const index_mcv = try self.resolveInst(bin_op.rhs);
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return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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const slice_ty = self.air.typeOf(bin_op.lhs);
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const elem_ty = slice_ty.childType();
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const elem_size = elem_ty.abiSize(self.target.*);
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var buf: Type.SlicePtrFieldTypeBuffer = undefined;
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const slice_ptr_field_type = slice_ty.slicePtrFieldType(&buf);
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const index_lock: ?RegisterLock = if (index_mcv == .register)
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self.register_manager.lockRegAssumeUnused(index_mcv.register)
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else
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null;
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defer if (index_lock) |reg| self.register_manager.unlockReg(reg);
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const base_mcv: MCValue = switch (slice_mcv) {
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.stack_offset => |off| .{ .register = try self.copyToTmpRegister(slice_ptr_field_type, .{ .stack_offset = off }) },
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else => return self.fail("TODO slice_elem_val when slice is {}", .{slice_mcv}),
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};
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const base_lock = self.register_manager.lockRegAssumeUnused(base_mcv.register);
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defer self.register_manager.unlockReg(base_lock);
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switch (elem_size) {
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else => {
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// TODO skip the ptr_add emission entirely and use native addressing modes
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// i.e sllx/mulx then R+R or scale immediate then R+I
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const dest = try self.allocRegOrMem(inst, true);
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const addr = try self.binOp(.ptr_add, null, base_mcv, index_mcv, slice_ptr_field_type, Type.usize);
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try self.load(dest, addr, slice_ptr_field_type);
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break :result dest;
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},
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}
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airSliceLen(self: *Self, inst: Air.Inst.Index) !void {
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@ -1407,6 +1440,18 @@ fn airSliceLen(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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fn airStore(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const ptr = try self.resolveInst(bin_op.lhs);
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const value = try self.resolveInst(bin_op.rhs);
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const ptr_ty = self.air.typeOf(bin_op.lhs);
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const value_ty = self.air.typeOf(bin_op.rhs);
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try self.store(ptr, value, ptr_ty, value_ty);
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return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
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_ = self;
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_ = inst;
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@ -1561,10 +1606,226 @@ fn binOp(
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}
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},
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.mul => {
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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// If LHS is immediate, then swap it with RHS.
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const lhs_is_imm = lhs == .immediate;
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const new_lhs = if (lhs_is_imm) rhs else lhs;
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const new_rhs = if (lhs_is_imm) lhs else rhs;
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const new_lhs_ty = if (lhs_is_imm) rhs_ty else lhs_ty;
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const new_rhs_ty = if (lhs_is_imm) lhs_ty else rhs_ty;
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// At this point, RHS might be an immediate
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// If it's a power of two immediate then we emit an shl instead
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// TODO add similar checks for LHS
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if (new_rhs == .immediate and math.isPowerOfTwo(new_rhs.immediate)) {
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return try self.binOp(.shl, maybe_inst, new_lhs, .{ .immediate = math.log2(new_rhs.immediate) }, new_lhs_ty, Type.usize);
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}
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return try self.binOpRegister(.mulx, maybe_inst, new_lhs, new_rhs, new_lhs_ty, new_rhs_ty);
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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}
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},
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else => unreachable,
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}
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},
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.ptr_add => {
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switch (lhs_ty.zigTypeTag()) {
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.Pointer => {
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const ptr_ty = lhs_ty;
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const elem_ty = switch (ptr_ty.ptrSize()) {
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.One => ptr_ty.childType().childType(), // ptr to array, so get array element type
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else => ptr_ty.childType(),
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};
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const elem_size = elem_ty.abiSize(self.target.*);
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if (elem_size == 1) {
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const base_tag: Mir.Inst.Tag = switch (tag) {
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.ptr_add => .add,
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else => unreachable,
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};
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return try self.binOpRegister(base_tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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} else {
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// convert the offset into a byte offset by
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// multiplying it with elem_size
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const offset = try self.binOp(.mul, null, rhs, .{ .immediate = elem_size }, Type.usize, Type.usize);
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const addr = try self.binOp(tag, null, lhs, offset, Type.initTag(.manyptr_u8), Type.usize);
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return addr;
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}
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},
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else => unreachable,
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}
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},
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.shl => {
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const base_tag: Air.Inst.Tag = switch (tag) {
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.shl => .shl_exact,
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else => unreachable,
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};
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// Generate a shl_exact/shr_exact
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const result = try self.binOp(base_tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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// Truncate if necessary
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switch (tag) {
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.shl => switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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const result_reg = result.register;
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try self.truncRegister(result_reg, result_reg, int_info.signedness, int_info.bits);
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return result;
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} else {
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return self.fail("TODO binary operations on integers > u64/i64", .{});
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}
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},
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else => unreachable,
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},
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else => unreachable,
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}
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},
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.shl_exact => {
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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const rhs_immediate_ok = rhs == .immediate;
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.shl_exact => .sllx,
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(mir_tag, maybe_inst, lhs, rhs, lhs_ty, false);
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} else {
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return try self.binOpRegister(mir_tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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}
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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}
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},
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else => unreachable,
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}
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},
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else => return self.fail("TODO implement {} binOp for SPARCv9", .{tag}),
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}
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}
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/// Don't call this function directly. Use binOp instead.
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///
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/// Calling this function signals an intention to generate a Mir
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/// instruction of the form
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///
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/// op dest, lhs, #rhs_imm
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///
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/// Set lhs_and_rhs_swapped to true iff inst.bin_op.lhs corresponds to
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/// rhs and vice versa. This parameter is only used when maybe_inst !=
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/// null.
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///
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/// Asserts that generating an instruction of that form is possible.
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fn binOpImmediate(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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lhs_and_rhs_swapped: bool,
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) !MCValue {
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const lhs_is_register = lhs == .register;
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const lhs_lock: ?RegisterLock = if (lhs_is_register)
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self.register_manager.lockReg(lhs.register)
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else
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null;
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defer if (lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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break :inst Air.refToIndex(
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if (lhs_and_rhs_swapped) bin_op.rhs else bin_op.lhs,
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).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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};
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const new_lhs_lock = self.register_manager.lockReg(lhs_reg);
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const dest_reg = switch (mir_tag) {
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else => if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (lhs_is_register and self.reuseOperand(
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inst,
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if (lhs_and_rhs_swapped) bin_op.rhs else bin_op.lhs,
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if (lhs_and_rhs_swapped) 1 else 0,
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lhs,
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)) {
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break :blk lhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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}
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} else blk: {
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break :blk try self.register_manager.allocReg(null);
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},
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};
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add,
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.mulx,
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.subcc,
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=> .{
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.arithmetic_3op = .{
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.is_imm = true,
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.rd = dest_reg,
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.rs1 = lhs_reg,
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.rs2_or_imm = .{ .imm = @intCast(i13, rhs.immediate) },
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},
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},
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.sllx => .{
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.shift = .{
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.is_imm = true,
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.width = ShiftWidth.shift64,
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.rd = dest_reg,
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.rs1 = lhs_reg,
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.rs2_or_imm = .{ .imm = @intCast(u6, rhs.immediate) },
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},
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},
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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/// Don't call this function directly. Use binOp instead.
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///
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/// Calling this function signals an intention to generate a Mir
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@ -1647,12 +1908,26 @@ fn binOpRegister(
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.subcc => .{ .arithmetic_3op = .{
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.is_imm = false,
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.rd = dest_reg,
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.rs1 = lhs_reg,
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.rs2_or_imm = .{ .rs2 = rhs_reg },
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} },
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.add,
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.mulx,
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.subcc,
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=> .{
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.arithmetic_3op = .{
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.is_imm = false,
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.rd = dest_reg,
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.rs1 = lhs_reg,
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.rs2_or_imm = .{ .rs2 = rhs_reg },
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},
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},
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.sllx => .{
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.shift = .{
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.is_imm = false,
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.width = ShiftWidth.shift64,
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.rd = dest_reg,
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.rs1 = lhs_reg,
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.rs2_or_imm = .{ .rs2 = rhs_reg },
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},
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},
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else => unreachable,
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};
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@ -2672,6 +2947,77 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
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}
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}
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fn truncRegister(
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self: *Self,
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operand_reg: Register,
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dest_reg: Register,
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int_signedness: std.builtin.Signedness,
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int_bits: u16,
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) !void {
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switch (int_bits) {
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1...31, 33...63 => {
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_ = try self.addInst(.{
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.tag = .sllx,
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.data = .{
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.shift = .{
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.is_imm = true,
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.width = ShiftWidth.shift64,
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.rd = dest_reg,
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.rs1 = operand_reg,
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.rs2_or_imm = .{ .imm = @intCast(u6, 64 - int_bits) },
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},
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},
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});
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_ = try self.addInst(.{
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.tag = switch (int_signedness) {
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.signed => .srax,
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.unsigned => .srlx,
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},
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.data = .{
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.shift = .{
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.is_imm = true,
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.width = ShiftWidth.shift32,
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.rd = dest_reg,
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.rs1 = dest_reg,
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.rs2_or_imm = .{ .imm = @intCast(u6, int_bits) },
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},
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},
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});
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},
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32 => {
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_ = try self.addInst(.{
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.tag = switch (int_signedness) {
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.signed => .sra,
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.unsigned => .srl,
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},
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.data = .{
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.shift = .{
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.is_imm = true,
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.width = ShiftWidth.shift32,
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.rd = dest_reg,
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.rs1 = operand_reg,
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.rs2_or_imm = .{ .imm = 0 },
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},
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},
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});
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},
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64 => {
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_ = try self.addInst(.{
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.tag = .@"or",
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.data = .{
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.arithmetic_3op = .{
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.is_imm = true,
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.rd = dest_reg,
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.rs1 = .g0,
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.rs2_or_imm = .{ .rs2 = operand_reg },
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},
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},
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});
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},
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else => unreachable,
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}
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}
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/// TODO support scope overrides. Also note this logic is duplicated with `Module.wantSafety`.
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fn wantSafety(self: *Self) bool {
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return switch (self.bin_file.options.optimize_mode) {
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@ -94,6 +94,8 @@ pub fn emitMir(
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.@"or" => try emit.mirArithmetic3Op(inst),
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.mulx => @panic("TODO implement sparc64 mulx"),
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.nop => try emit.mirNop(),
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.@"return" => try emit.mirArithmetic2Op(inst),
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@ -103,7 +105,12 @@ pub fn emitMir(
|
||||
|
||||
.sethi => try emit.mirSethi(inst),
|
||||
|
||||
.sll => @panic("TODO implement sparc64 sll"),
|
||||
.srl => @panic("TODO implement sparc64 srl"),
|
||||
.sra => @panic("TODO implement sparc64 sra"),
|
||||
.sllx => @panic("TODO implement sparc64 sllx"),
|
||||
.srlx => @panic("TODO implement sparc64 srlx"),
|
||||
.srax => @panic("TODO implement sparc64 srax"),
|
||||
|
||||
.stb => try emit.mirArithmetic3Op(inst),
|
||||
.sth => try emit.mirArithmetic3Op(inst),
|
||||
|
||||
@ -74,6 +74,11 @@ pub const Inst = struct {
|
||||
// TODO add other operations.
|
||||
@"or",
|
||||
|
||||
/// A.37 Multiply and Divide (64-bit)
|
||||
/// This uses the arithmetic_3op field.
|
||||
// TODO add other operations.
|
||||
mulx,
|
||||
|
||||
/// A.40 No Operation
|
||||
/// This uses the nop field.
|
||||
nop,
|
||||
@ -93,8 +98,12 @@ pub const Inst = struct {
|
||||
|
||||
/// A.49 Shift
|
||||
/// This uses the shift field.
|
||||
// TODO add other operations.
|
||||
sll,
|
||||
srl,
|
||||
sra,
|
||||
sllx,
|
||||
srlx,
|
||||
srax,
|
||||
|
||||
/// A.54 Store Integer
|
||||
/// This uses the arithmetic_3op field.
|
||||
@ -210,7 +219,7 @@ pub const Inst = struct {
|
||||
/// if is_imm true then it uses the imm field of rs2_or_imm,
|
||||
/// otherwise it uses rs2 field.
|
||||
///
|
||||
/// Used by e.g. add, sub
|
||||
/// Used by e.g. sllx
|
||||
shift: struct {
|
||||
is_imm: bool,
|
||||
width: Instruction.ShiftWidth,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user