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stage2: sparc64: Implement SPARCv9 subcc

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This commit is contained in:
Koakuma 2022-05-02 21:56:04 +07:00
parent 2770f9a034
commit 5d260eb573
2 changed files with 11 additions and 1 deletions
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4
src/arch/sparc64/Emit.zig
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@ -81,7 +81,7 @@ pub fn emitMir(
.stx => try emit.mirArithmetic3Op(inst),
.sub => try emit.mirArithmetic3Op(inst),
.subcc => @panic("TODO implement sparcv9 subcc"),
.subcc => try emit.mirArithmetic3Op(inst),
.tcc => try emit.mirTrap(inst),
}
@ -169,6 +169,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
.stw => try emit.writeInstruction(Instruction.stw(i13, rs1, imm, rd)),
.stx => try emit.writeInstruction(Instruction.stx(i13, rs1, imm, rd)),
.sub => try emit.writeInstruction(Instruction.sub(i13, rs1, imm, rd)),
.subcc => try emit.writeInstruction(Instruction.subcc(i13, rs1, imm, rd)),
else => unreachable,
}
} else {
@ -188,6 +189,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
.stw => try emit.writeInstruction(Instruction.stw(Register, rs1, rs2, rd)),
.stx => try emit.writeInstruction(Instruction.stx(Register, rs1, rs2, rd)),
.sub => try emit.writeInstruction(Instruction.sub(Register, rs1, rs2, rd)),
.subcc => try emit.writeInstruction(Instruction.subcc(Register, rs1, rs2, rd)),
else => unreachable,
}
}

8
src/arch/sparc64/bits.zig
View File

@ -1261,6 +1261,14 @@ pub const Instruction = union(enum) {
};
}
pub fn subcc(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
return switch (s2) {
Register => format3a(0b10, 0b01_0100, rs1, rs2, rd),
i13 => format3b(0b10, 0b01_0100, rs1, rs2, rd),
else => unreachable,
};
}
pub fn trap(comptime s2: type, cond: ICondition, ccr: CCR, rs1: Register, rs2: s2) Instruction {
// Tcc instructions abuse the rd field to store the conditionals.
return switch (s2) {