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stage2: sparc64: Implement airLoad/airStore
This commit is contained in:
Koakuma
parent
0b54649cac
commit
8f8853cd4f
@ -563,7 +563,7 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.is_non_err_ptr => @panic("TODO try self.airIsNonErrPtr(inst)"),
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.is_err => try self.airIsErr(inst),
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.is_err_ptr => @panic("TODO try self.airIsErrPtr(inst)"),
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.load => @panic("TODO try self.airLoad(inst)"),
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.load => try self.airLoad(inst),
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.loop => @panic("TODO try self.airLoop(inst)"),
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.not => @panic("TODO try self.airNot(inst)"),
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.ptrtoint => @panic("TODO try self.airPtrToInt(inst)"),
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@ -1242,6 +1242,36 @@ fn airIsNonErr(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ un_op, .none, .none });
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}
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fn airLoad(self: *Self, inst: Air.Inst.Index) !void {
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const ty_op = self.air.instructions.items(.data)[inst].ty_op;
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const elem_ty = self.air.typeOfIndex(inst);
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const elem_size = elem_ty.abiSize(self.target.*);
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const result: MCValue = result: {
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if (!elem_ty.hasRuntimeBits())
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break :result MCValue.none;
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const ptr = try self.resolveInst(ty_op.operand);
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const is_volatile = self.air.typeOf(ty_op.operand).isVolatilePtr();
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if (self.liveness.isUnused(inst) and !is_volatile)
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break :result MCValue.dead;
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const dst_mcv: MCValue = blk: {
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if (elem_size <= 8 and self.reuseOperand(inst, ty_op.operand, 0, ptr)) {
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// The MCValue that holds the pointer can be re-used as the value.
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break :blk switch (ptr) {
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.register => |r| MCValue{ .register = r },
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else => ptr,
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};
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} else {
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break :blk try self.allocRegOrMem(inst, true);
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}
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};
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try self.load(dst_mcv, ptr, self.air.typeOf(ty_op.operand));
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break :result dst_mcv;
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};
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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fn airRet(self: *Self, inst: Air.Inst.Index) !void {
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const un_op = self.air.instructions.items(.data)[inst].un_op;
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const operand = try self.resolveInst(un_op);
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@ -1263,10 +1293,15 @@ fn airRetPtr(self: *Self, inst: Air.Inst.Index) !void {
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}
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fn airStore(self: *Self, inst: Air.Inst.Index) !void {
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_ = self;
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_ = inst;
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const ptr = try self.resolveInst(bin_op.lhs);
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const value = try self.resolveInst(bin_op.rhs);
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const ptr_ty = self.air.typeOf(bin_op.lhs);
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const value_ty = self.air.typeOf(bin_op.rhs);
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return self.fail("TODO implement store for {}", .{self.target.cpu.arch});
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try self.store(ptr, value, ptr_ty, value_ty);
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return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
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@ -1522,6 +1557,76 @@ fn genArgDbgInfo(self: *Self, inst: Air.Inst.Index, mcv: MCValue, arg_index: u32
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}
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}
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// TODO replace this to call to extern memcpy
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fn genInlineMemcpy(
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self: *Self,
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src: Register,
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dst: Register,
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len: Register,
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tmp: Register,
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) !void {
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// Here we assume that len > 0.
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// Also we do the copy from end -> start address to save a register.
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// sub len, 1, len
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_ = try self.addInst(.{
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.tag = .sub,
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.data = .{ .arithmetic_3op = .{
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.is_imm = true,
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.rs1 = len,
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.rs2_or_imm = .{ .imm = 1 },
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.rd = len,
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} },
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});
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// loop:
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// ldub [src + len], tmp
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_ = try self.addInst(.{
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.tag = .ldub,
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.data = .{ .arithmetic_3op = .{
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.is_imm = false,
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.rs1 = src,
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.rs2_or_imm = .{ .rs2 = len },
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.rd = tmp,
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} },
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});
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// stb tmp, [dst + len]
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_ = try self.addInst(.{
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.tag = .stb,
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.data = .{ .arithmetic_3op = .{
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.is_imm = false,
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.rs1 = dst,
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.rs2_or_imm = .{ .rs2 = len },
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.rd = tmp,
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} },
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});
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// brnz len, loop
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_ = try self.addInst(.{
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.tag = .bpr,
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.data = .{ .branch_predict_reg = .{
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.cond = .ne_zero,
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.rs1 = len,
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.inst = @intCast(u32, self.mir_instructions.len - 2),
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} },
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});
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// Delay slot:
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// sub len, 1, len
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_ = try self.addInst(.{
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.tag = .sub,
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.data = .{ .arithmetic_3op = .{
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.is_imm = true,
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.rs1 = len,
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.rs2_or_imm = .{ .imm = 1 },
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.rd = len,
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} },
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});
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// end:
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}
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fn genLoad(self: *Self, value_reg: Register, addr_reg: Register, comptime off_type: type, off: off_type, abi_size: u64) !void {
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assert(off_type == Register or off_type == i13);
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@ -1913,6 +2018,66 @@ fn iterateBigTomb(self: *Self, inst: Air.Inst.Index, operand_count: usize) !BigT
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};
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}
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fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!void {
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const elem_ty = ptr_ty.elemType();
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const elem_size = elem_ty.abiSize(self.target.*);
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switch (ptr) {
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.none => unreachable,
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.undef => unreachable,
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.unreach => unreachable,
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.dead => unreachable,
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.compare_flags_unsigned,
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.compare_flags_signed,
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=> unreachable, // cannot hold an address
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.immediate => |imm| try self.setRegOrMem(elem_ty, dst_mcv, .{ .memory = imm }),
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.ptr_stack_offset => |off| try self.setRegOrMem(elem_ty, dst_mcv, .{ .stack_offset = off }),
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.register => |addr_reg| {
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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switch (dst_mcv) {
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.dead => unreachable,
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.undef => unreachable,
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.compare_flags_signed, .compare_flags_unsigned => unreachable,
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.register => |dst_reg| {
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try self.genLoad(dst_reg, addr_reg, i13, 0, elem_size);
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},
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.stack_offset => |off| {
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if (elem_size <= 8) {
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const tmp_reg = try self.register_manager.allocReg(null);
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self.register_manager.freezeRegs(&.{tmp_reg});
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defer self.register_manager.unfreezeRegs(&.{tmp_reg});
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try self.load(.{ .register = tmp_reg }, ptr, ptr_ty);
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try self.genSetStack(elem_ty, off, MCValue{ .register = tmp_reg });
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} else {
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const regs = try self.register_manager.allocRegs(3, .{ null, null, null });
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self.register_manager.freezeRegs(®s);
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defer self.register_manager.unfreezeRegs(®s);
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const src_reg = addr_reg;
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const dst_reg = regs[0];
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const len_reg = regs[1];
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const tmp_reg = regs[2];
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try self.genSetReg(ptr_ty, dst_reg, .{ .ptr_stack_offset = off });
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try self.genSetReg(Type.usize, len_reg, .{ .immediate = elem_size });
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try self.genInlineMemcpy(src_reg, dst_reg, len_reg, tmp_reg);
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}
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},
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else => return self.fail("TODO load from register into {}", .{dst_mcv}),
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}
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},
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.memory,
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.stack_offset,
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=> {
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const addr_reg = try self.copyToTmpRegister(ptr_ty, ptr);
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try self.load(dst_mcv, .{ .register = addr_reg }, ptr_ty);
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},
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}
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}
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fn lowerDeclRef(self: *Self, tv: TypedValue, decl_index: Module.Decl.Index) InnerError!MCValue {
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const ptr_bits = self.target.cpu.arch.ptrBitWidth();
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const ptr_bytes: u64 = @divExact(ptr_bits, 8);
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@ -2167,6 +2332,45 @@ pub fn spillInstruction(self: *Self, reg: Register, inst: Air.Inst.Index) !void
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try self.genSetStack(self.air.typeOfIndex(inst), stack_mcv.stack_offset, reg_mcv);
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}
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fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type) InnerError!void {
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const abi_size = value_ty.abiSize(self.target.*);
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switch (ptr) {
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.none => unreachable,
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.undef => unreachable,
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.unreach => unreachable,
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.dead => unreachable,
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.compare_flags_unsigned,
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.compare_flags_signed,
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=> unreachable, // cannot hold an address
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.immediate => |imm| {
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try self.setRegOrMem(value_ty, .{ .memory = imm }, value);
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},
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.ptr_stack_offset => |off| {
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try self.genSetStack(value_ty, off, value);
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},
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.register => |addr_reg| {
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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switch (value) {
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.register => |value_reg| {
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try self.genStore(value_reg, addr_reg, i13, 0, abi_size);
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},
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else => {
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return self.fail("TODO implement copying of memory", .{});
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},
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}
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},
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.memory,
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.stack_offset,
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=> {
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const addr_reg = try self.copyToTmpRegister(ptr_ty, ptr);
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try self.store(.{ .register = addr_reg }, value, ptr_ty, value_ty);
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},
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}
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}
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/// TODO support scope overrides. Also note this logic is duplicated with `Module.wantSafety`.
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fn wantSafety(self: *Self) bool {
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return switch (self.bin_file.options.optimize_mode) {
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