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stage2: sparc64: Implement airCmp
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Koakuma
parent
ae2d6b7eea
commit
0c8ce9ed9d
@ -521,12 +521,12 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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.div_float, .div_trunc, .div_floor, .div_exact => try self.airDiv(inst),
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.cmp_lt => @panic("TODO try self.airCmp(inst, .lt)"),
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.cmp_lte => @panic("TODO try self.airCmp(inst, .lte)"),
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.cmp_eq => @panic("TODO try self.airCmp(inst, .eq)"),
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.cmp_gte => @panic("TODO try self.airCmp(inst, .gte)"),
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.cmp_gt => @panic("TODO try self.airCmp(inst, .gt)"),
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.cmp_neq => @panic("TODO try self.airCmp(inst, .neq)"),
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.cmp_lt => try self.airCmp(inst, .lt),
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.cmp_lte => try self.airCmp(inst, .lte),
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.cmp_eq => try self.airCmp(inst, .eq),
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.cmp_gte => try self.airCmp(inst, .gte),
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.cmp_gt => try self.airCmp(inst, .gt),
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.cmp_neq => try self.airCmp(inst, .neq),
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.cmp_vector => @panic("TODO try self.airCmpVector(inst)"),
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.cmp_lt_errors_len => @panic("TODO try self.airCmpLtErrorsLen(inst)"),
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@ -996,6 +996,54 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
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@panic("TODO handle return value with BigTomb");
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}
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fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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var int_buffer: Type.Payload.Bits = undefined;
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const int_ty = switch (lhs_ty.zigTypeTag()) {
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.Vector => unreachable, // Should be handled by cmp_vector?
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.Enum => lhs_ty.intTagType(&int_buffer),
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.Int => lhs_ty,
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.Bool => Type.initTag(.u1),
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.Pointer => Type.usize,
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.ErrorSet => Type.initTag(.u16),
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.Optional => blk: {
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var opt_buffer: Type.Payload.ElemType = undefined;
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const payload_ty = lhs_ty.optionalChild(&opt_buffer);
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if (!payload_ty.hasRuntimeBitsIgnoreComptime()) {
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break :blk Type.initTag(.u1);
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} else if (lhs_ty.isPtrLikeOptional()) {
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break :blk Type.usize;
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} else {
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return self.fail("TODO SPARCv9 cmp non-pointer optionals", .{});
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}
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},
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.Float => return self.fail("TODO SPARCv9 cmp floats", .{}),
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else => unreachable,
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};
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const int_info = int_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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_ = try self.binOp(.cmp_eq, inst, lhs, rhs, int_ty, int_ty);
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try self.spillCompareFlagsIfOccupied();
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self.compare_flags_inst = inst;
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break :result switch (int_info.signedness) {
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.signed => MCValue{ .compare_flags_signed = op },
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.unsigned => MCValue{ .compare_flags_unsigned = op },
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};
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} else {
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return self.fail("TODO SPARCv9 cmp for ints > 64 bits", .{});
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}
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
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const pl_op = self.air.instructions.items(.data)[inst].pl_op;
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const cond = try self.resolveInst(pl_op.operand);
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@ -1427,6 +1475,149 @@ fn allocRegOrMem(self: *Self, inst: Air.Inst.Index, reg_ok: bool) !MCValue {
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return MCValue{ .stack_offset = stack_offset };
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}
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/// For all your binary operation needs, this function will generate
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/// the corresponding Mir instruction(s). Returns the location of the
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/// result.
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///
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/// If the binary operation itself happens to be an Air instruction,
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/// pass the corresponding index in the inst parameter. That helps
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/// this function do stuff like reusing operands.
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///
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/// This function does not do any lowering to Mir itself, but instead
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/// looks at the lhs and rhs and determines which kind of lowering
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/// would be best suitable and then delegates the lowering to other
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/// functions.
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fn binOp(
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self: *Self,
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tag: Air.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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) InnerError!MCValue {
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const mod = self.bin_file.options.module.?;
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switch (tag) {
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.cmp_eq => {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO binary operations on floats", .{}),
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int => {
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assert(lhs_ty.eql(rhs_ty, mod));
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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// TODO optimize for small (i13) values by putting them inside immediates
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.cmp_eq => .subcc,
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else => unreachable,
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};
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return try self.binOpRegister(mir_tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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}
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},
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else => unreachable,
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}
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},
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else => return self.fail("TODO implement {} binOp for SPARCv9", .{tag}),
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}
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}
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/// Don't call this function directly. Use binOp instead.
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///
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/// Calling this function signals an intention to generate a Mir
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/// instruction of the form
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///
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/// op dest, lhs, rhs
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///
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/// Asserts that generating an instruction of that form is possible.
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fn binOpRegister(
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self: *Self,
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mir_tag: Mir.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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) !MCValue {
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
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if (rhs_is_register) self.register_manager.freezeRegs(&.{rhs.register});
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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break :inst Air.refToIndex(bin_op.lhs).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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self.register_manager.freezeRegs(&.{reg});
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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};
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defer self.register_manager.unfreezeRegs(&.{lhs_reg});
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const rhs_reg = if (rhs_is_register) rhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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break :inst Air.refToIndex(bin_op.rhs).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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self.register_manager.freezeRegs(&.{reg});
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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};
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defer self.register_manager.unfreezeRegs(&.{rhs_reg});
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const dest_reg = switch (mir_tag) {
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else => if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (lhs_is_register and self.reuseOperand(inst, bin_op.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else if (rhs_is_register and self.reuseOperand(inst, bin_op.rhs, 1, rhs)) {
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break :blk rhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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}
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} else blk: {
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break :blk try self.register_manager.allocReg(null);
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},
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};
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.subcc => .{ .arithmetic_3op = .{
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.is_imm = false,
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.rd = dest_reg,
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.rs1 = lhs_reg,
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.rs2_or_imm = .{ .rs2 = rhs_reg },
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} },
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = mir_data,
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});
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return MCValue{ .register = dest_reg };
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}
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fn br(self: *Self, block: Air.Inst.Index, operand: Air.Inst.Ref) !void {
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const block_data = self.blocks.getPtr(block).?;
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@ -2146,6 +2337,9 @@ fn processDeath(self: *Self, inst: Air.Inst.Index) void {
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.register => |reg| {
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self.register_manager.freeReg(reg);
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},
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.compare_flags_signed, .compare_flags_unsigned => {
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self.compare_flags_inst = null;
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},
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else => {}, // TODO process stack allocation death
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}
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}
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@ -2338,6 +2532,29 @@ fn setRegOrMem(self: *Self, ty: Type, loc: MCValue, val: MCValue) !void {
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}
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}
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/// Save the current instruction stored in the compare flags if
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/// occupied
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fn spillCompareFlagsIfOccupied(self: *Self) !void {
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if (self.compare_flags_inst) |inst_to_save| {
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const mcv = self.getResolvedInstValue(inst_to_save);
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switch (mcv) {
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.compare_flags_signed,
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.compare_flags_unsigned,
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=> {},
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else => unreachable, // mcv doesn't occupy the compare flags
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}
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const new_mcv = try self.allocRegOrMem(inst_to_save, true);
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try self.setRegOrMem(self.air.typeOfIndex(inst_to_save), new_mcv, mcv);
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log.debug("spilling {d} to mcv {any}", .{ inst_to_save, new_mcv });
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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try branch.inst_table.put(self.gpa, inst_to_save, new_mcv);
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self.compare_flags_inst = null;
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}
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}
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pub fn spillInstruction(self: *Self, reg: Register, inst: Air.Inst.Index) !void {
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const stack_mcv = try self.allocRegOrMem(inst, false);
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log.debug("spilling {d} to stack mcv {any}", .{ inst, stack_mcv });
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@ -115,6 +115,10 @@ pub const Inst = struct {
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/// A.61 Trap on Integer Condition Codes (Tcc)
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/// This uses the trap field.
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tcc,
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// TODO add synthetic instructions
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// TODO add cmp synthetic instruction to avoid wasting a register when
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// comparing with subcc
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};
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/// The position of an MIR instruction within the `Mir` instructions array.
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