582 Commits

Author SHA1 Message Date
joachimschmidt557
c2d2307d09 stage2 AArch64: initial implementation of {add,sub}_with_overflow 2022-05-05 21:43:35 +02:00
Andrew Kelley
44252f4d35 LLVM: fix C ABI for windows
* sret logic needed a check for hasRuntimeBits()
 * lower f128 on windows targets with the "sse" class rather than
   "memory". For reference, clang emits a compile error when __float128
   is used with the MSVC ABI, saying that this type is not supported.
   The docs for the x64 calling convention have both of these sentences:
   - "Any argument that doesn't fit in 8 bytes, or isn't 1, 2, 4, or 8 bytes,
     must be passed by reference."
   - "All floating point operations are done using the 16 XMM registers."
 * For i128, however, it is clear that the Windows calling convention
   wants such an object to be passed by reference. I fixed the LLVM
   lowering for function parameters to make this work.
2022-05-04 22:57:57 -07:00
Andrew Kelley
3cfde183f3
Merge pull request #11571 from ziglang/stage2-test-behavior
progress towards stage2 behavior tests for all targets passing with the LLVM backend
2022-05-03 14:58:46 -04:00
Jakub Konka
d48789467d x86_64: use math.zig to check isPowerOfTwo and calc log2_int 2022-05-03 16:39:21 +02:00
Andrew Kelley
65389dc280 stage2: improve inline asm stage1 compatibility
* outputs can have names and be referenced with template replacements
   the same as inputs.
 * fix print_air.zig not decoding correctly.
 * LLVM backend: use a table for template names for simplicity
2022-05-02 22:14:17 -07:00
Andrew Kelley
09f1d62bdf add new builtin function @tan
The reason for having `@tan` is that we already have `@sin` and `@cos`
because some targets have machine code instructions for them, but in the
case that the implementation needs to go into compiler-rt, sin, cos, and
tan all share a common dependency which includes a table of data. To
avoid duplicating this table of data, we promote tan to become a builtin
alongside sin and cos.

ZIR: The tag enum is at capacity so this commit moves
`field_call_bind_named` to be `extended`. I measured this as one of
the least used tags in the zig codebase.

Fix libc math suffix for `f32` being wrong in both stage1 and stage2.
stage1: add missing libc prefix for float functions.
2022-04-27 16:45:23 -07:00
Luuk de Gram
5f2d0d414d wasm: Implement codegen for C-ABI
This implements passing arguments and storing return values correctly
for the C-ABI as specified by the tool-convention:
https://github.com/WebAssembly/tool-conventions/blob/main/BasicCABI.md

There's definitely room for better codegen in follow-up commits.
2022-04-26 12:20:27 +02:00
Luuk de Gram
cb49af6c9a wasm: Initial C-ABI implementation
This implements the C-ABI convention as specified by:
https://github.com/WebAssembly/tool-conventions/blob/main/BasicCABI.md
While not an official specification, it's the ABI that is output by clang/LLVM.
As we use LLVM to compile compiler-rt, and want to integrate with C-libraries,
we follow the same convention when the calling convention results in 'C'.
2022-04-26 12:20:27 +02:00
Andrew Kelley
9c5fe5b5a4 LLVM: C calling convention lowering fixes
For parameters and return types of functions with the C calling
convention, the LLVM backend now has a special lowering for the function
type that makes the function adhere to the C ABI. The AIR instruction
lowerings for call, ret, and ret_load are adjusted to bitcast the real
type to the ABI type if necessary.

More work on this will need to be done, however, this improvement is
enough that stage3 now passes all the same behavior tests that stage2
passes - notably, translate-c no longer has a segfault due to C ABI
issues with Zig's Clang C API wrapper.
2022-04-21 20:27:06 -07:00
Andrew Kelley
f7596ae942 stage2: use indexes for Decl objects
Rather than allocating Decl objects with an Allocator, we instead allocate
them with a SegmentedList. This provides four advantages:
 * Stable memory so that one thread can access a Decl object while another
   thread allocates additional Decl objects from this list.
 * It allows us to use u32 indexes to reference Decl objects rather than
   pointers, saving memory in Type, Value, and dependency sets.
 * Using integers to reference Decl objects rather than pointers makes
   serialization trivial.
 * It provides a unique integer to be used for anonymous symbol names,
   avoiding multi-threaded contention on an atomic counter.
2022-04-20 17:37:35 -07:00
joachimschmidt557
fa85a739d9
stage2 AArch64: fix shl, shr, shl_exact, shr_exact
Introduces the necessary truncation after shift
2022-04-19 22:40:51 +02:00
joachimschmidt557
cbb13c023e
stage2 AArch64: change binOp lowering mechanism to use Mir tags
Mirrors e2e69803dc16efe11a6d42c6c49853e16a41fd0c for AArch64
2022-04-19 22:40:50 +02:00
joachimschmidt557
0a909a6712
stage2 AArch64: implement addwrap, subwrap, mulwrap 2022-04-19 22:40:50 +02:00
joachimschmidt557
d9d9fea6ae
stage2 AArch64: Add ldrsb, ldrsh instructions 2022-04-19 22:40:48 +02:00
joachimschmidt557
f95a8ddafa
stage2 AArch64: Implement basic truncate functionality 2022-04-19 22:39:14 +02:00
joachimschmidt557
c78daeb642
stage2 AArch64: add basic assertions to bits.zig for correct codegen
Includes many fixes of errors discovered by adding these assertions
2022-04-19 22:37:56 +02:00
Andrew Kelley
9c2cbe39c2
Merge pull request #11461 from Luukdegram/wasm-debug-info
Wasm: add support for debug information
2022-04-19 14:12:13 -04:00
Luuk de Gram
be08d2bdbd
wasm: Fix unreachable paths
When the last instruction is a debug instruction, the type of it is void.
Similarly for 'noreturn' emit an 'unreachable' instruction to tell the wasm-validator
the path cannot be reached.

Also respect the '--strip' flag in the self-hosted wasm linker and not emit a 'name' section
when the flag is set to `true`.
2022-04-19 19:58:49 +02:00
Andrew Kelley
535d5624e4 wasm: fix lowerDeclRefValue using wrong Decl 2022-04-19 13:04:59 -04:00
joachimschmidt557
3bfb1616db stage2 ARM: move genArgDbgInfo back to CodeGen
This removes the questionable Air -> Mir dependency that existed
before. The x86_64 backend also performed this change.
2022-04-16 09:41:27 +02:00
Andrew Kelley
4c83b11f71
Merge pull request #11438 from Vexu/stage2-fixes
Stage2 fixes
2022-04-15 12:02:55 -04:00
Jakub Konka
52c8ac1a84 stage2: lower u128, and refactor some bits in x64 2022-04-15 11:50:08 -04:00
Veikka Tuominen
6ad510d832 update self hosted sources to language changes 2022-04-15 11:17:19 +03:00
Jakub Konka
2635e4ca6e
Merge pull request #11434 from koachan/sparc64-codegen 2022-04-14 21:38:35 +02:00
Andrew Kelley
2587474717 stage2: progress towards stage3
* The `@bitCast` workaround is removed in favor of `@ptrCast` properly
   doing element casting for slice element types. This required an
   enhancement both to stage1 and stage2.
 * stage1 incorrectly accepts `.{}` instead of `{}`. stage2 code that
   abused this is fixed.
 * Make some parameters comptime to support functions in switch
   expressions (as opposed to making them function pointers).
 * Avoid relying on local temporaries being mutable.
 * Workarounds for when stage1 and stage2 disagree on function pointer
   types.
 * Workaround recursive formatting bug with a `@panic("TODO")`.
 * Remove unreachable `else` prongs for some inferred error sets.

All in effort towards #89.
2022-04-14 10:12:45 -07:00
Koakuma
c07213269f stage2: zig fmt 2022-04-14 23:26:03 +07:00
Koakuma
9201fbe85b stage2: sparcv9: Add cmp_lt_errors_len AIR inst & fix asm parsing 2022-04-14 22:34:51 +07:00
Koakuma
b916ba18b6 stage2: sparcv9: Fix Tcc encoding 2022-04-14 22:18:06 +07:00
Koakuma
dcb12a7941 stage2: sparcv9: Use regular structs to encode instructions
Currently packed structs still has endian-dependent behavior, so it results
in code that is not portable across platforms (see also issue 10113).
2022-04-14 22:18:06 +07:00
Koakuma
1467590e40 stage2: sparcv9: Implement enough instruction to compile simple exes 2022-04-14 22:18:06 +07:00
Koakuma
cfd389f927 stage2: sparcv9: zig fmt 2022-04-14 22:18:06 +07:00
Flandre Scarlet
ab2ea9fb09 stage2: sparcv9: Test failure error logging 2022-04-14 22:18:06 +07:00
Koakuma
7051970ad7 stage2: sparcv9: implement basic instruction lowering 2022-04-14 22:18:06 +07:00
Koakuma
5e2045cbe5 stage2: sparcv9: Implement basic asm codegen 2022-04-14 22:18:06 +07:00
Koakuma
42f4bd3421 stage2: sparcv9: Add breakpoint, ret, and calling mechanism 2022-04-14 22:18:06 +07:00
Koakuma
1972a2b080 stage2: sparcv9: Add placeholders to generate a minimal program 2022-04-14 22:18:06 +07:00
Koakuma
cec48f2cf1 stage2: sparcv9: Different formatting for genBody 2022-04-14 22:18:06 +07:00
Koakuma
5ab6b5a777 stage2: sparcv9: implement dbgAdvancePCAndLine 2022-04-14 22:18:06 +07:00
Koakuma
71cd3466ec stage2: sparcv9: Adjust RegisterManager settings 2022-04-14 22:18:06 +07:00
Koakuma
18c98eb429 stage2: sparcv9: Placeholder for Air instructions in genBody 2022-04-14 22:18:06 +07:00
Koakuma
94d70bdb69 stage2: sparcv9: Change ordering in Mir Tag 2022-04-14 22:18:05 +07:00
Koakuma
94a84e783e stage2: sparcv9: Implement basic prologue/epilogue Mir emission 2022-04-14 22:18:05 +07:00
Koakuma
927706e6d0 stage2: sparcv9: Emit debug inst placeholder 2022-04-14 22:18:05 +07:00
Koakuma
cf13356dab stage2: sparcv9: Mir extraData implementation 2022-04-14 22:18:05 +07:00
Koakuma
1ba5227216 stage2: sparcv9: Initial resolveCallingConventionValues implementation 2022-04-14 22:18:05 +07:00
Koakuma
a5a89fde13 stage2: sparcv9: Add skeleton codegen impl and necessary fields 2022-04-14 22:18:05 +07:00
Koakuma
a30688ef2a stage2: sparcv9: Add some initial checks in codegen 2022-04-14 22:18:05 +07:00
Jakub Konka
edb428fae4 macho,x64: resolve debug info relocs for RIP-based addressing
Sometimes we will want to generate debug info for a constant that
has been lowered to memory and not copied anywhere else. For this
we will need to defer resolution on PIE platforms until all locals
(including GOT entries) have been allocated.
2022-04-13 19:50:23 +02:00
Jakub Konka
3f912430bd stage2,x64: deref memory if referenced via GOT for local vars 2022-04-13 16:24:56 +02:00
Jakub Konka
4c50a27d68 stage2,x64: generate debug info for local vars at hardcoded mem addr 2022-04-13 14:31:04 +02:00