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stage2 AArch64: change binOp lowering mechanism to use Mir tags
Mirrors e2e69803dc16efe11a6d42c6c49853e16a41fd0c for AArch64
This commit is contained in:
joachimschmidt557
parent
0a909a6712
commit
cbb13c023e
@ -1193,7 +1193,7 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {
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/// Asserts that generating an instruction of that form is possible.
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fn binOpRegister(
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self: *Self,
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tag: Air.Inst.Tag,
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mir_tag: Mir.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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@ -1256,38 +1256,9 @@ fn binOpRegister(
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add,
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.ptr_add,
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=> .add_shifted_register,
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.sub,
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.ptr_sub,
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=> .sub_shifted_register,
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.cmp_eq => .cmp_shifted_register,
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.mul => .mul,
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.bit_and,
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.bool_and,
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=> .and_shifted_register,
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.bit_or,
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.bool_or,
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=> .orr_shifted_register,
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.shl,
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.shl_exact,
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=> .lsl_register,
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.shr,
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.shr_exact,
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=> switch (lhs_ty.intInfo(self.target.*).signedness) {
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.signed => Mir.Inst.Tag.asr_register,
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.unsigned => Mir.Inst.Tag.lsr_register,
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},
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.xor => .eor_shifted_register,
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else => unreachable,
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};
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const mir_data: Mir.Inst.Data = switch (tag) {
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.add,
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.sub,
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.ptr_add,
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.ptr_sub,
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add_shifted_register,
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.sub_shifted_register,
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=> .{ .rrr_imm6_shift = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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@ -1295,27 +1266,24 @@ fn binOpRegister(
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.imm6 = 0,
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.shift = .lsl,
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} },
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.cmp_eq => .{ .rr_imm6_shift = .{
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.cmp_shifted_register => .{ .rr_imm6_shift = .{
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.rn = lhs_reg,
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.rm = rhs_reg,
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.imm6 = 0,
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.shift = .lsl,
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} },
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.mul,
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.shl,
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.shl_exact,
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.shr,
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.shr_exact,
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.lsl_register,
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.asr_register,
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.lsr_register,
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=> .{ .rrr = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.rm = rhs_reg,
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} },
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.bit_and,
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.bool_and,
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.bit_or,
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.bool_or,
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.xor,
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.and_shifted_register,
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.orr_shifted_register,
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.eor_shifted_register,
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=> .{ .rrr_imm6_logical_shift = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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@ -1348,7 +1316,7 @@ fn binOpRegister(
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/// Asserts that generating an instruction of that form is possible.
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fn binOpImmediate(
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self: *Self,
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tag: Air.Inst.Tag,
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mir_tag: Mir.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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lhs: MCValue,
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rhs: MCValue,
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@ -1379,8 +1347,8 @@ fn binOpImmediate(
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};
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defer self.register_manager.unfreezeRegs(&.{lhs_reg});
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const dest_reg = switch (tag) {
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.cmp_eq => undefined, // cmp has no destination register
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const dest_reg = switch (mir_tag) {
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.cmp_immediate => undefined, // cmp has no destination register
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else => if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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@ -1400,39 +1368,23 @@ fn binOpImmediate(
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add_immediate,
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.sub => .sub_immediate,
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.shl,
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.shl_exact,
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=> .lsl_immediate,
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.shr,
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.shr_exact,
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=> switch (lhs_ty.intInfo(self.target.*).signedness) {
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.signed => Mir.Inst.Tag.asr_immediate,
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.unsigned => Mir.Inst.Tag.lsr_immediate,
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},
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.cmp_eq => .cmp_immediate,
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else => unreachable,
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};
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const mir_data: Mir.Inst.Data = switch (tag) {
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.add,
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.sub,
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const mir_data: Mir.Inst.Data = switch (mir_tag) {
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.add_immediate,
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.sub_immediate,
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=> .{ .rr_imm12_sh = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.imm12 = @intCast(u12, rhs.immediate),
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} },
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.shl,
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.shl_exact,
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.shr,
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.shr_exact,
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.lsl_immediate,
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.asr_immediate,
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.lsr_immediate,
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=> .{ .rr_shift = .{
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.rd = dest_reg,
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.rn = lhs_reg,
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.shift = @intCast(u6, rhs.immediate),
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} },
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.cmp_eq => .{ .r_imm12_sh = .{
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.cmp_immediate => .{ .r_imm12_sh = .{
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.rn = lhs_reg,
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.imm12 = @intCast(u12, rhs.immediate),
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} },
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@ -1470,7 +1422,6 @@ fn binOp(
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) InnerError!MCValue {
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const target = self.target.*;
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switch (tag) {
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// Arithmetic operations on integers and floats
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.add,
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.sub,
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.cmp_eq,
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@ -1498,13 +1449,26 @@ fn binOp(
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else => unreachable,
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};
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const mir_tag_register: Mir.Inst.Tag = switch (tag) {
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.add => .add_shifted_register,
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.sub => .sub_shifted_register,
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.cmp_eq => .cmp_shifted_register,
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else => unreachable,
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};
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const mir_tag_immediate: Mir.Inst.Tag = switch (tag) {
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.add => .add_immediate,
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.sub => .sub_immediate,
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.cmp_eq => .cmp_immediate,
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(tag, maybe_inst, lhs, rhs, lhs_ty, false);
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return try self.binOpImmediate(mir_tag_immediate, maybe_inst, lhs, rhs, lhs_ty, false);
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} else if (lhs_immediate_ok) {
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// swap lhs and rhs
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return try self.binOpImmediate(tag, maybe_inst, rhs, lhs, rhs_ty, true);
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return try self.binOpImmediate(mir_tag_immediate, maybe_inst, rhs, lhs, rhs_ty, true);
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} else {
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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return try self.binOpRegister(mir_tag_register, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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}
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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@ -1523,7 +1487,7 @@ fn binOp(
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// TODO add optimisations for multiplication
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// with immediates, for example a * 2 can be
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// lowered to a << 1
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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return try self.binOpRegister(.mul, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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}
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@ -1564,7 +1528,6 @@ fn binOp(
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else => unreachable,
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}
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},
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// Bitwise operations on integers
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.bit_and,
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.bit_or,
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.xor,
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@ -1576,7 +1539,14 @@ fn binOp(
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const int_info = lhs_ty.intInfo(self.target.*);
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if (int_info.bits <= 64) {
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// TODO implement bitwise operations with immediates
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.bit_and => .and_shifted_register,
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.bit_or => .orr_shifted_register,
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.xor => .eor_shifted_register,
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else => unreachable,
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};
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return try self.binOpRegister(mir_tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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}
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@ -1594,10 +1564,27 @@ fn binOp(
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if (int_info.bits <= 64) {
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const rhs_immediate_ok = rhs == .immediate;
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const mir_tag_register: Mir.Inst.Tag = switch (tag) {
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.shl => .lsl_register,
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.shr => switch (lhs_ty.intInfo(self.target.*).signedness) {
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.signed => Mir.Inst.Tag.asr_register,
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.unsigned => Mir.Inst.Tag.lsr_register,
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},
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else => unreachable,
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};
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const mir_tag_immediate: Mir.Inst.Tag = switch (tag) {
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.shl => .lsl_immediate,
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.shr => switch (lhs_ty.intInfo(self.target.*).signedness) {
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.signed => Mir.Inst.Tag.asr_immediate,
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.unsigned => Mir.Inst.Tag.lsr_immediate,
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},
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else => unreachable,
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};
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if (rhs_immediate_ok) {
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return try self.binOpImmediate(tag, maybe_inst, lhs, rhs, lhs_ty, false);
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return try self.binOpImmediate(mir_tag_immediate, maybe_inst, lhs, rhs, lhs_ty, false);
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} else {
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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return try self.binOpRegister(mir_tag_register, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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}
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} else {
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return self.fail("TODO binary operations on int with bits > 64", .{});
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@ -1614,7 +1601,13 @@ fn binOp(
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assert(lhs != .immediate); // should have been handled by Sema
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assert(rhs != .immediate); // should have been handled by Sema
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return try self.binOpRegister(tag, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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const mir_tag_register: Mir.Inst.Tag = switch (tag) {
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.bool_and => .and_shifted_register,
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.bool_or => .orr_shifted_register,
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else => unreachable,
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};
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return try self.binOpRegister(mir_tag_register, maybe_inst, lhs, rhs, lhs_ty, rhs_ty);
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},
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else => unreachable,
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}
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@ -1632,9 +1625,9 @@ fn binOp(
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const elem_size = elem_ty.abiSize(self.target.*);
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if (elem_size == 1) {
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const base_tag: Air.Inst.Tag = switch (tag) {
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.ptr_add => .add,
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.ptr_sub => .sub,
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const base_tag: Mir.Inst.Tag = switch (tag) {
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.ptr_add => .add_shifted_register,
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.ptr_sub => .sub_shifted_register,
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else => unreachable,
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};
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