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stage2 AArch64: add basic assertions to bits.zig for correct codegen
Includes many fixes of errors discovered by adding these assertions
This commit is contained in:
joachimschmidt557
parent
9c2cbe39c2
commit
c78daeb642
@ -376,7 +376,7 @@ fn gen(self: *Self) !void {
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// mov fp, sp
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_ = try self.addInst(.{
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.tag = .mov_to_from_sp,
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.data = .{ .rr = .{ .rd = .x29, .rn = .xzr } },
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.data = .{ .rr = .{ .rd = .x29, .rn = .sp } },
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});
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// sub sp, sp, #reloc
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@ -421,7 +421,7 @@ fn gen(self: *Self) !void {
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if (math.cast(u12, stack_size)) |size| {
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self.mir_instructions.set(backpatch_reloc, .{
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.tag = .sub_immediate,
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.data = .{ .rr_imm12_sh = .{ .rd = .xzr, .rn = .xzr, .imm12 = size } },
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.data = .{ .rr_imm12_sh = .{ .rd = .sp, .rn = .sp, .imm12 = size } },
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});
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} else |_| {
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return self.failSymbol("TODO AArch64: allow larger stacks", .{});
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@ -453,7 +453,7 @@ fn gen(self: *Self) !void {
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// add sp, sp, #stack_size
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_ = try self.addInst(.{
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.tag = .add_immediate,
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.data = .{ .rr_imm12_sh = .{ .rd = .xzr, .rn = .xzr, .imm12 = @intCast(u12, stack_size) } },
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.data = .{ .rr_imm12_sh = .{ .rd = .sp, .rn = .sp, .imm12 = @intCast(u12, stack_size) } },
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});
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// <load other registers>
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@ -882,7 +882,8 @@ fn spillCompareFlagsIfOccupied(self: *Self) !void {
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/// allocated. A second call to `copyToTmpRegister` may return the same register.
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/// This can have a side effect of spilling instructions to the stack to free up a register.
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fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
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const reg = try self.register_manager.allocReg(null);
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const raw_reg = try self.register_manager.allocReg(null);
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const reg = registerAlias(raw_reg, ty.abiSize(self.target.*));
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try self.genSetReg(ty, reg, mcv);
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return reg;
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}
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@ -891,7 +892,9 @@ fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
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/// `reg_owner` is the instruction that gets associated with the register in the register table.
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/// This can have a side effect of spilling instructions to the stack to free up a register.
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fn copyToNewRegister(self: *Self, reg_owner: Air.Inst.Index, mcv: MCValue) !MCValue {
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const reg = try self.register_manager.allocReg(reg_owner);
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const raw_reg = try self.register_manager.allocReg(reg_owner);
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const ty = self.air.typeOfIndex(reg_owner);
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const reg = registerAlias(raw_reg, ty.abiSize(self.target.*));
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try self.genSetReg(self.air.typeOfIndex(reg_owner), reg, mcv);
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return MCValue{ .register = reg };
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}
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@ -1003,7 +1006,8 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
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break :blk op_reg;
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}
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break :blk try self.register_manager.allocReg(null);
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const raw_reg = try self.register_manager.allocReg(null);
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break :blk raw_reg.to32();
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};
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_ = try self.addInst(.{
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@ -1013,7 +1017,7 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
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.rn = op_reg,
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.imms = 0b000000,
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.immr = 0b000000,
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.n = 0b1,
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.n = 0b0,
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} },
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});
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@ -1035,7 +1039,8 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
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break :blk op_reg;
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}
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break :blk try self.register_manager.allocReg(null);
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const raw_reg = try self.register_manager.allocReg(null);
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break :blk registerAlias(raw_reg, operand_ty.abiSize(self.target.*));
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};
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_ = try self.addInst(.{
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@ -1124,7 +1129,8 @@ fn binOpRegister(
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break :inst Air.refToIndex(bin_op.lhs).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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const raw_reg = try self.register_manager.allocReg(track_inst);
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const reg = registerAlias(raw_reg, lhs_ty.abiSize(self.target.*));
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self.register_manager.freezeRegs(&.{reg});
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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@ -1139,7 +1145,8 @@ fn binOpRegister(
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break :inst Air.refToIndex(bin_op.rhs).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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const raw_reg = try self.register_manager.allocReg(track_inst);
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const reg = registerAlias(raw_reg, rhs_ty.abiAlignment(self.target.*));
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self.register_manager.freezeRegs(&.{reg});
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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@ -1156,7 +1163,8 @@ fn binOpRegister(
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} else if (rhs_is_register and self.reuseOperand(inst, bin_op.rhs, 1, rhs)) {
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break :blk rhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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const raw_reg = try self.register_manager.allocReg(inst);
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break :blk registerAlias(raw_reg, lhs_ty.abiSize(self.target.*));
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}
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} else try self.register_manager.allocReg(null);
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@ -1276,7 +1284,8 @@ fn binOpImmediate(
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).?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst);
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const raw_reg = try self.register_manager.allocReg(track_inst);
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const reg = registerAlias(raw_reg, lhs_ty.abiSize(self.target.*));
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self.register_manager.freezeRegs(&.{reg});
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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@ -1298,7 +1307,8 @@ fn binOpImmediate(
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)) {
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break :blk lhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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const raw_reg = try self.register_manager.allocReg(inst);
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break :blk registerAlias(raw_reg, lhs_ty.abiSize(self.target.*));
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}
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} else try self.register_manager.allocReg(null),
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};
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@ -1965,7 +1975,8 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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},
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.stack_offset => |off| {
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if (elem_size <= 8) {
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const tmp_reg = try self.register_manager.allocReg(null);
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const raw_tmp_reg = try self.register_manager.allocReg(null);
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const tmp_reg = registerAlias(raw_tmp_reg, elem_size);
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self.register_manager.freezeRegs(&.{tmp_reg});
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defer self.register_manager.unfreezeRegs(&.{tmp_reg});
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@ -2001,12 +2012,8 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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.got_load,
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.direct_load,
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=> {
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const reg = try self.register_manager.allocReg(null);
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self.register_manager.freezeRegs(&.{reg});
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defer self.register_manager.unfreezeRegs(&.{reg});
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try self.genSetReg(ptr_ty, reg, ptr);
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try self.load(dst_mcv, .{ .register = reg }, ptr_ty);
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const addr_reg = try self.copyToTmpRegister(ptr_ty, ptr);
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try self.load(dst_mcv, .{ .register = addr_reg }, ptr_ty);
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},
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}
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}
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@ -2091,6 +2098,7 @@ fn genInlineMemcpy(
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fn airLoad(self: *Self, inst: Air.Inst.Index) !void {
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const ty_op = self.air.instructions.items(.data)[inst].ty_op;
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const elem_ty = self.air.typeOfIndex(inst);
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const elem_size = elem_ty.abiSize(self.target.*);
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const result: MCValue = result: {
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if (!elem_ty.hasRuntimeBits())
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break :result MCValue.none;
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@ -2101,9 +2109,12 @@ fn airLoad(self: *Self, inst: Air.Inst.Index) !void {
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break :result MCValue.dead;
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const dst_mcv: MCValue = blk: {
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if (self.reuseOperand(inst, ty_op.operand, 0, ptr)) {
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if (elem_size <= 8 and self.reuseOperand(inst, ty_op.operand, 0, ptr)) {
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// The MCValue that holds the pointer can be re-used as the value.
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break :blk ptr;
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break :blk switch (ptr) {
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.register => |r| MCValue{ .register = registerAlias(r, elem_size) },
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else => ptr,
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};
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} else {
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break :blk try self.allocRegOrMem(inst, true);
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}
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@ -2209,6 +2220,8 @@ fn genStrRegister(self: *Self, value_reg: Register, addr_reg: Register, abi_size
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}
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fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type) InnerError!void {
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const abi_size = value_ty.abiSize(self.target.*);
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switch (ptr) {
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.none => unreachable,
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.undef => unreachable,
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@ -2226,14 +2239,14 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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const abi_size = value_ty.abiSize(self.target.*);
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switch (value) {
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.register => |value_reg| {
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try self.genStrRegister(value_reg, addr_reg, abi_size);
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},
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else => {
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if (abi_size <= 8) {
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const tmp_reg = try self.register_manager.allocReg(null);
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const raw_tmp_reg = try self.register_manager.allocReg(null);
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const tmp_reg = registerAlias(raw_tmp_reg, abi_size);
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self.register_manager.freezeRegs(&.{tmp_reg});
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defer self.register_manager.unfreezeRegs(&.{tmp_reg});
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@ -3522,8 +3535,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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.memory => |addr| {
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// The value is in memory at a hard-coded address.
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// If the type is a pointer, it means the pointer address is at this memory location.
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try self.genSetReg(ty, reg, .{ .immediate = addr });
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try self.genLdrRegister(reg, reg, ty.abiSize(self.target.*));
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try self.genSetReg(ty, reg.to64(), .{ .immediate = addr });
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try self.genLdrRegister(reg, reg.to64(), ty.abiSize(self.target.*));
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},
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.stack_offset => |off| {
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const abi_size = ty.abiSize(self.target.*);
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@ -3998,6 +4011,12 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type) !CallMCValues {
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var nsaa: u32 = 0; // Next stacked argument address
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for (param_types) |ty, i| {
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const param_size = @intCast(u32, ty.abiSize(self.target.*));
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if (param_size == 0) {
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result.args[i] = .{ .none = {} };
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continue;
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}
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// We round up NCRN only for non-Apple platforms which allow the 16-byte aligned
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// values to spread across odd-numbered registers.
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if (ty.abiAlignment(self.target.*) == 16 and !self.target.isDarwin()) {
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@ -4005,10 +4024,9 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type) !CallMCValues {
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ncrn += ncrn % 2;
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}
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const param_size = @intCast(u32, ty.abiSize(self.target.*));
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if (std.math.divCeil(u32, param_size, 8) catch unreachable <= 8 - ncrn) {
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if (param_size <= 8) {
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result.args[i] = .{ .register = c_abi_int_param_regs[ncrn] };
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result.args[i] = .{ .register = registerAlias(c_abi_int_param_regs[ncrn], param_size) };
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ncrn += 1;
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} else {
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return self.fail("TODO MCValues with multiple registers", .{});
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@ -4045,7 +4063,7 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type) !CallMCValues {
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.Unspecified, .C => {
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const ret_ty_size = @intCast(u32, ret_ty.abiSize(self.target.*));
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if (ret_ty_size <= 8) {
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result.return_value = .{ .register = c_abi_int_return_regs[0] };
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result.return_value = .{ .register = registerAlias(c_abi_int_return_regs[0], ret_ty_size) };
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} else {
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return self.fail("TODO support more return types for ARM backend", .{});
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}
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@ -457,8 +457,13 @@ fn mirAddSubtractImmediate(emit: *Emit, inst: Mir.Inst.Index) !void {
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const rn = r_imm12_sh.rn;
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const imm12 = r_imm12_sh.imm12;
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const sh = r_imm12_sh.sh == 1;
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const zr: Register = switch (rn.size()) {
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32 => .wzr,
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64 => .xzr,
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else => unreachable,
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};
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try emit.writeInstruction(Instruction.subs(.xzr, rn, imm12, sh));
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try emit.writeInstruction(Instruction.subs(zr, rn, imm12, sh));
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},
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else => unreachable,
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}
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@ -674,8 +679,13 @@ fn mirAddSubtractShiftedRegister(emit: *Emit, inst: Mir.Inst.Index) !void {
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const rm = rr_imm6_shift.rm;
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const shift = rr_imm6_shift.shift;
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const imm6 = rr_imm6_shift.imm6;
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const zr: Register = switch (rn.size()) {
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32 => .wzr,
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64 => .xzr,
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else => unreachable,
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};
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try emit.writeInstruction(Instruction.subsShiftedRegister(.xzr, rn, rm, shift, imm6));
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try emit.writeInstruction(Instruction.subsShiftedRegister(zr, rn, rm, shift, imm6));
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},
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else => unreachable,
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}
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@ -686,7 +696,12 @@ fn mirConditionalSelect(emit: *Emit, inst: Mir.Inst.Index) !void {
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switch (tag) {
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.cset => {
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const r_cond = emit.mir.instructions.items(.data)[inst].r_cond;
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try emit.writeInstruction(Instruction.csinc(r_cond.rd, .xzr, .xzr, r_cond.cond));
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const zr: Register = switch (r_cond.rd.size()) {
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32 => .wzr,
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64 => .xzr,
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else => unreachable,
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};
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try emit.writeInstruction(Instruction.csinc(r_cond.rd, zr, zr, r_cond.cond));
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},
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else => unreachable,
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}
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@ -718,14 +733,14 @@ fn mirLoadMemoryPie(emit: *Emit, inst: Mir.Inst.Index) !void {
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// PC-relative displacement to the entry in memory.
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// adrp
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const offset = @intCast(u32, emit.code.items.len);
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try emit.writeInstruction(Instruction.adrp(reg, 0));
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try emit.writeInstruction(Instruction.adrp(reg.to64(), 0));
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switch (tag) {
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.load_memory_got => {
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// ldr reg, reg, offset
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try emit.writeInstruction(Instruction.ldr(
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reg,
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reg,
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reg.to64(),
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Instruction.LoadStoreOffset.imm(0),
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));
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},
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@ -739,11 +754,11 @@ fn mirLoadMemoryPie(emit: *Emit, inst: Mir.Inst.Index) !void {
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// Note that this can potentially be optimised out by the codegen/linker if the
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// target address is appropriately aligned.
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// add reg, reg, offset
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try emit.writeInstruction(Instruction.add(reg, reg, 0, false));
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try emit.writeInstruction(Instruction.add(reg.to64(), reg.to64(), 0, false));
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// ldr reg, reg, offset
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try emit.writeInstruction(Instruction.ldr(
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reg,
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reg,
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reg.to64(),
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Instruction.LoadStoreOffset.imm(0),
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));
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},
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@ -905,7 +920,13 @@ fn mirMoveRegister(emit: *Emit, inst: Mir.Inst.Index) !void {
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switch (tag) {
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.mov_register => {
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const rr = emit.mir.instructions.items(.data)[inst].rr;
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try emit.writeInstruction(Instruction.orrShiftedRegister(rr.rd, .xzr, rr.rn, .lsl, 0));
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const zr: Register = switch (rr.rd.size()) {
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32 => .wzr,
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64 => .xzr,
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else => unreachable,
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};
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try emit.writeInstruction(Instruction.orrShiftedRegister(rr.rd, zr, rr.rn, .lsl, 0));
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},
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.mov_to_from_sp => {
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const rr = emit.mir.instructions.items(.data)[inst].rr;
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@ -917,8 +938,13 @@ fn mirMoveRegister(emit: *Emit, inst: Mir.Inst.Index) !void {
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const rm = rr_imm6_logical_shift.rm;
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const shift = rr_imm6_logical_shift.shift;
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const imm6 = rr_imm6_logical_shift.imm6;
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const zr: Register = switch (rd.size()) {
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32 => .wzr,
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64 => .xzr,
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else => unreachable,
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};
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try emit.writeInstruction(Instruction.ornShiftedRegister(rd, .xzr, rm, shift, imm6));
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try emit.writeInstruction(Instruction.ornShiftedRegister(rd, zr, rm, shift, imm6));
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},
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else => unreachable,
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}
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@ -695,6 +695,9 @@ pub const Instruction = union(enum) {
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offset: LoadStoreOffset,
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variant: LoadStoreVariant,
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) Instruction {
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assert(rn.size() == 64);
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assert(rn.id() != Register.xzr.id());
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const off = offset.toU12();
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const op1: u2 = blk: {
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switch (offset) {
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@ -741,6 +744,9 @@ pub const Instruction = union(enum) {
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encoding: u2,
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load: bool,
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) Instruction {
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assert(rn.size() == 64);
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assert(rn.id() != Register.xzr.id());
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switch (rt1.size()) {
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32 => {
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assert(-256 <= offset and offset <= 252);
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@ -849,38 +855,26 @@ pub const Instruction = union(enum) {
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shift: LogicalShiftedRegisterShift,
|
||||
amount: u6,
|
||||
) Instruction {
|
||||
switch (rd.size()) {
|
||||
32 => {
|
||||
assert(amount < 32);
|
||||
return Instruction{
|
||||
.logical_shifted_register = .{
|
||||
.rd = rd.enc(),
|
||||
.rn = rn.enc(),
|
||||
.imm6 = amount,
|
||||
.rm = rm.enc(),
|
||||
.n = n,
|
||||
.shift = @enumToInt(shift),
|
||||
.opc = opc,
|
||||
.sf = 0b0,
|
||||
},
|
||||
};
|
||||
assert(rd.size() == rn.size());
|
||||
assert(rd.size() == rm.size());
|
||||
if (rd.size() == 32) assert(amount < 32);
|
||||
|
||||
return Instruction{
|
||||
.logical_shifted_register = .{
|
||||
.rd = rd.enc(),
|
||||
.rn = rn.enc(),
|
||||
.imm6 = amount,
|
||||
.rm = rm.enc(),
|
||||
.n = n,
|
||||
.shift = @enumToInt(shift),
|
||||
.opc = opc,
|
||||
.sf = switch (rd.size()) {
|
||||
32 => 0b0,
|
||||
64 => 0b1,
|
||||
else => unreachable,
|
||||
},
|
||||
},
|
||||
64 => {
|
||||
return Instruction{
|
||||
.logical_shifted_register = .{
|
||||
.rd = rd.enc(),
|
||||
.rn = rn.enc(),
|
||||
.imm6 = amount,
|
||||
.rm = rm.enc(),
|
||||
.n = n,
|
||||
.shift = @enumToInt(shift),
|
||||
.opc = opc,
|
||||
.sf = 0b1,
|
||||
},
|
||||
};
|
||||
},
|
||||
else => unreachable, // unexpected register size
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
fn addSubtractImmediate(
|
||||
@ -891,6 +885,9 @@ pub const Instruction = union(enum) {
|
||||
imm12: u12,
|
||||
shift: bool,
|
||||
) Instruction {
|
||||
assert(rd.size() == rn.size());
|
||||
assert(rn.id() != Register.xzr.id());
|
||||
|
||||
return Instruction{
|
||||
.add_subtract_immediate = .{
|
||||
.rd = rd.enc(),
|
||||
@ -916,6 +913,9 @@ pub const Instruction = union(enum) {
|
||||
immr: u6,
|
||||
n: u1,
|
||||
) Instruction {
|
||||
assert(rd.size() == rn.size());
|
||||
assert(!(rd.size() == 32 and n == 1));
|
||||
|
||||
return Instruction{
|
||||
.logical_immediate = .{
|
||||
.rd = rd.enc(),
|
||||
@ -941,6 +941,8 @@ pub const Instruction = union(enum) {
|
||||
immr: u6,
|
||||
imms: u6,
|
||||
) Instruction {
|
||||
assert(rd.size() == rn.size());
|
||||
|
||||
return Instruction{
|
||||
.bitfield = .{
|
||||
.rd = rd.enc(),
|
||||
@ -969,6 +971,9 @@ pub const Instruction = union(enum) {
|
||||
rm: Register,
|
||||
imm6: u6,
|
||||
) Instruction {
|
||||
assert(rd.size() == rn.size());
|
||||
assert(rd.size() == rm.size());
|
||||
|
||||
return Instruction{
|
||||
.add_subtract_shifted_register = .{
|
||||
.rd = rd.enc(),
|
||||
@ -994,6 +999,7 @@ pub const Instruction = union(enum) {
|
||||
offset: i21,
|
||||
) Instruction {
|
||||
assert(offset & 0b11 == 0b00);
|
||||
|
||||
return Instruction{
|
||||
.conditional_branch = .{
|
||||
.cond = @enumToInt(cond),
|
||||
@ -1010,6 +1016,7 @@ pub const Instruction = union(enum) {
|
||||
offset: i21,
|
||||
) Instruction {
|
||||
assert(offset & 0b11 == 0b00);
|
||||
|
||||
return Instruction{
|
||||
.compare_and_branch = .{
|
||||
.rt = rt.enc(),
|
||||
@ -1033,6 +1040,9 @@ pub const Instruction = union(enum) {
|
||||
rm: Register,
|
||||
cond: Condition,
|
||||
) Instruction {
|
||||
assert(rd.size() == rn.size());
|
||||
assert(rd.size() == rm.size());
|
||||
|
||||
return Instruction{
|
||||
.conditional_select = .{
|
||||
.rd = rd.enc(),
|
||||
@ -1085,6 +1095,9 @@ pub const Instruction = union(enum) {
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
) Instruction {
|
||||
assert(rd.size() == rn.size());
|
||||
assert(rd.size() == rm.size());
|
||||
|
||||
return Instruction{
|
||||
.data_processing_2_source = .{
|
||||
.rd = rd.enc(),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user