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stage2: sparcv9: Adjust RegisterManager settings

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This commit is contained in:
Koakuma 2022-04-01 22:23:19 +07:00
parent 18c98eb429
commit 71cd3466ec
2 changed files with 20 additions and 4 deletions
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5
src/arch/sparcv9/CodeGen.zig
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@ -16,6 +16,8 @@ const Type = @import("../../type.zig").Type;
const GenerateSymbolError = @import("../../codegen.zig").GenerateSymbolError;
const FnResult = @import("../../codegen.zig").FnResult;
const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
const RegisterManagerFn = @import("../../register_manager.zig").RegisterManager;
const RegisterManager = RegisterManagerFn(Self, Register, &abi.allocatable_regs);
const build_options = @import("build_options");
@ -73,6 +75,8 @@ branch_stack: *std.ArrayList(Branch),
// Key is the block instruction
blocks: std.AutoHashMapUnmanaged(Air.Inst.Index, BlockData) = .{},
register_manager: RegisterManager = .{},
/// Maps offset to what is stored there.
stack: std.AutoHashMapUnmanaged(u32, StackAllocation) = .{},
@ -380,7 +384,6 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type, is_caller: bool) !Ca
return result;
}
/// Caller must call `CallMCValues.deinit`.
fn gen(self: *Self) !void {
const cc = self.fn_type.fnCallingConvention();
if (cc != .Naked) {

19
src/arch/sparcv9/abi.zig
View File

@ -1,9 +1,22 @@
const bits = @import("bits.zig");
const Register = bits.Register;
// Register windowing mechanism will take care of preserving registers
// so no need to do it manually
pub const callee_preserved_regs = [_]Register{};
// There are no callee-preserved registers since the windowing
// mechanism already takes care of them.
// We still need to preserve %o0-%o5, %g1, %g4, and %g5 before calling
// something, though, as those are shared with the callee and might be
// thrashed by it.
pub const caller_preserved_regs = [_]Register{ .o0, .o1, .o2, .o3, .o4, .o5, .g1, .g4, .g5 };
// Try to allocate i, l, o, then g sets of registers, in order of priority.
pub const allocatable_regs = [_]Register{
// zig fmt: off
.@"i0", .@"i1", .@"i2", .@"i3", .@"i4", .@"i5",
.l0, .l1, .l2, .l3, .l4, .l5, .l6, .l7,
.o0, .o1, .o2, .o3, .o4, .o5,
.g1, .g4, .g5,
// zig fmt: on
};
pub const c_abi_int_param_regs_caller_view = [_]Register{ .o0, .o1, .o2, .o3, .o4, .o5 };
pub const c_abi_int_param_regs_callee_view = [_]Register{ .@"i0", .@"i1", .@"i2", .@"i3", .@"i4", .@"i5" };