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stage2: sparcv9: Emit debug inst placeholder
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@ -7,6 +7,7 @@ const Module = @import("../../Module.zig");
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const ErrorMsg = Module.ErrorMsg;
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const Liveness = @import("../../Liveness.zig");
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const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
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const DW = std.dwarf;
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const Emit = @This();
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const Mir = @import("Mir.zig");
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@ -33,11 +34,60 @@ const InnerError = error{
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pub fn emitMir(
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emit: *Emit,
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) InnerError!void {
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_ = emit;
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const mir_tags = emit.mir.instructions.items(.tag);
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@panic("TODO implement emitMir");
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// Emit machine code
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for (mir_tags) |tag, index| {
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const inst = @intCast(u32, index);
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switch (tag) {
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.dbg_line => try emit.mirDbgLine(inst),
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.dbg_prologue_end => try emit.mirDebugPrologueEnd(),
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.dbg_epilogue_begin => try emit.mirDebugEpilogueBegin(),
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}
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}
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}
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pub fn deinit(emit: *Emit) void {
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emit.* = undefined;
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}
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fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
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_ = self;
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_ = line;
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_ = column;
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@panic("TODO implement dbgAdvancePCAndLine");
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}
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fn mirDbgLine(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const dbg_line_column = emit.mir.instructions.items(.data)[inst].dbg_line_column;
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switch (tag) {
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.dbg_line => try emit.dbgAdvancePCAndLine(dbg_line_column.line, dbg_line_column.column),
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else => unreachable,
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}
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}
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fn mirDebugPrologueEnd(self: *Emit) !void {
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switch (self.debug_output) {
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.dwarf => |dbg_out| {
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try dbg_out.dbg_line.append(DW.LNS.set_prologue_end);
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try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
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},
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.plan9 => {},
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.none => {},
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}
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}
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fn mirDebugEpilogueBegin(self: *Emit) !void {
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switch (self.debug_output) {
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.dwarf => |dbg_out| {
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try dbg_out.dbg_line.append(DW.LNS.set_epilogue_begin);
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try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
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},
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.plan9 => {},
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.none => {},
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}
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}
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