From 927706e6d0cf289be979bb6f12be6636c0e07f59 Mon Sep 17 00:00:00 2001
From: Koakuma <koachan@protonmail.com>
Date: Tue, 29 Mar 2022 20:54:23 +0700
Subject: [PATCH] stage2: sparcv9: Emit debug inst placeholder

---
 src/arch/sparcv9/Emit.zig | 54 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 2 deletions(-)

diff --git a/src/arch/sparcv9/Emit.zig b/src/arch/sparcv9/Emit.zig
index 1821570701..2587b94c7c 100644
--- a/src/arch/sparcv9/Emit.zig
+++ b/src/arch/sparcv9/Emit.zig
@@ -7,6 +7,7 @@ const Module = @import("../../Module.zig");
 const ErrorMsg = Module.ErrorMsg;
 const Liveness = @import("../../Liveness.zig");
 const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
+const DW = std.dwarf;
 
 const Emit = @This();
 const Mir = @import("Mir.zig");
@@ -33,11 +34,60 @@ const InnerError = error{
 pub fn emitMir(
     emit: *Emit,
 ) InnerError!void {
-    _ = emit;
+    const mir_tags = emit.mir.instructions.items(.tag);
 
-    @panic("TODO implement emitMir");
+    // Emit machine code
+    for (mir_tags) |tag, index| {
+        const inst = @intCast(u32, index);
+        switch (tag) {
+            .dbg_line => try emit.mirDbgLine(inst),
+
+            .dbg_prologue_end => try emit.mirDebugPrologueEnd(),
+            .dbg_epilogue_begin => try emit.mirDebugEpilogueBegin(),
+        }
+    }
 }
 
 pub fn deinit(emit: *Emit) void {
     emit.* = undefined;
 }
+
+fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
+    _ = self;
+    _ = line;
+    _ = column;
+
+    @panic("TODO implement dbgAdvancePCAndLine");
+}
+
+fn mirDbgLine(emit: *Emit, inst: Mir.Inst.Index) !void {
+    const tag = emit.mir.instructions.items(.tag)[inst];
+    const dbg_line_column = emit.mir.instructions.items(.data)[inst].dbg_line_column;
+
+    switch (tag) {
+        .dbg_line => try emit.dbgAdvancePCAndLine(dbg_line_column.line, dbg_line_column.column),
+        else => unreachable,
+    }
+}
+
+fn mirDebugPrologueEnd(self: *Emit) !void {
+    switch (self.debug_output) {
+        .dwarf => |dbg_out| {
+            try dbg_out.dbg_line.append(DW.LNS.set_prologue_end);
+            try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
+        },
+        .plan9 => {},
+        .none => {},
+    }
+}
+
+fn mirDebugEpilogueBegin(self: *Emit) !void {
+    switch (self.debug_output) {
+        .dwarf => |dbg_out| {
+            try dbg_out.dbg_line.append(DW.LNS.set_epilogue_begin);
+            try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
+        },
+        .plan9 => {},
+        .none => {},
+    }
+}