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stage2: sparcv9: Fix Tcc encoding

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This commit is contained in:
Koakuma 2022-04-13 19:39:21 +07:00
parent dcb12a7941
commit b916ba18b6
1 changed files with 1 additions and 1 deletions
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src/arch/sparcv9/bits.zig
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@ -1061,7 +1061,7 @@ pub const Instruction = union(enum) {
// Tcc instructions abuse the rd field to store the conditionals.
return switch (s2) {
Register => format4a(0b11_1010, ccr, rs1, rs2, @intToEnum(Register, cond)),
u7 => format4e(0b00_0100, ccr, rs1, @intToEnum(Register, cond), rs2),
u7 => format4e(0b11_1010, ccr, rs1, @intToEnum(Register, cond), rs2),
else => unreachable,
};
}