From b916ba18b6ace62fccc74eb11205946842bba66b Mon Sep 17 00:00:00 2001
From: Koakuma <koachan@protonmail.com>
Date: Wed, 13 Apr 2022 19:39:21 +0700
Subject: [PATCH] stage2: sparcv9: Fix Tcc encoding

---
 src/arch/sparcv9/bits.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/sparcv9/bits.zig b/src/arch/sparcv9/bits.zig
index 3e62b68572..bc8b8822b7 100644
--- a/src/arch/sparcv9/bits.zig
+++ b/src/arch/sparcv9/bits.zig
@@ -1061,7 +1061,7 @@ pub const Instruction = union(enum) {
         // Tcc instructions abuse the rd field to store the conditionals.
         return switch (s2) {
             Register => format4a(0b11_1010, ccr, rs1, rs2, @intToEnum(Register, cond)),
-            u7 => format4e(0b00_0100, ccr, rs1, @intToEnum(Register, cond), rs2),
+            u7 => format4e(0b11_1010, ccr, rs1, @intToEnum(Register, cond), rs2),
             else => unreachable,
         };
     }