29243 Commits

Author SHA1 Message Date
David Rubin
ece70e08a0 riscv: pass optionals by register_pair for resolveCallingConventionValues 2024-05-11 02:17:11 -07:00
David Rubin
26ce82d98e riscv: correctly derefence load_symbol in genSetReg 2024-05-11 02:17:11 -07:00
David Rubin
3bf008a3d0 riscv: implement slices 2024-05-11 02:17:11 -07:00
David Rubin
350ad90cee riscv: totally rewrite how we do loads and stores
this commit is a little too large to document fully, however the main gist of it this

- finish the `genInlineMemcpy` implement
- rename `setValue` to `genCopy` as I agree with jacob that it's a better name
- add in `genVarDbgInfo` for a better gdb experience
- follow the x86_64's method for genCall, as the procedure is very similar for us
- add `airSliceLen` as it's trivial
- change up the `airAddWithOverflow implementation a bit
- make sure to not spill of the elem_ty is 0 size
- correctly follow the RISC-V calling convention and spill the used calle saved registers in the prologue
and restore them in the epilogue
- add `address`, `deref`, and `offset` helper functions for MCValue. I must say I love these,
they make the code very readable and super verbose :)
- fix a `register_manager.zig` issue where when using the last register in the set, the value would overflow at comptime.
was happening because we were adding to `max_id` before subtracting from it.
2024-05-11 02:17:11 -07:00
David Rubin
cbf62bd6dc riscv: switch default_panic to use the message 2024-05-11 02:17:11 -07:00
David Rubin
3c0015c828 riscv: implement a basic @intCast
the truncation panic logic is generated in Sema, so I don't need to roll anything
of my own. I add all of the boilerplate for that detecting the truncation and it works
in basic test cases!
2024-05-11 02:17:11 -07:00
David Rubin
685f828218 riscv: add a custom panic function
this provides a much better indication of when we are having a controlled panic with an error message
or when we are actually segfaulting, as before the `trap` as causing a segfault.
2024-05-11 02:17:11 -07:00
David Rubin
b28c966e33 riscv: fix overflow checks in addition. 2024-05-11 02:17:11 -07:00
David Rubin
e70584e2f8 riscv: change load_symbol psuedo instruction size to 8 2024-05-11 02:17:11 -07:00
David Rubin
06089fc89a riscv: fix how we calculate stack offsets. allows for pass by reference arguments. 2024-05-11 02:17:11 -07:00
David Rubin
c96989aa4b riscv: correctly index struct field access
when the struct is in stack memory, we access it using a byte-offset,
because that's how the stack works. on the other hand when the struct
is in a register, we are working with bits and the field offset should
be a bit offset.
2024-05-11 02:17:11 -07:00
David Rubin
09b7aabe09 riscv: add allocReg helper, and clean up some comparing logic
- Added the basic framework for panicing with an overflow in `airAddWithOverflow`, but there is no check done yet.
- added the `cmp_lt`, `cmp_gte`, and `cmp_imm_eq` MIR instructions, and their respective functionality.
2024-05-11 02:17:11 -07:00
David Rubin
08452b1add riscv: correct the order of the return epilogue 2024-05-11 02:17:11 -07:00
David Rubin
f1fe5c937e riscv: pointer work
lots of thinking later, ive begun to grasp my head around how the pointers should work. this commit allows basic pointer loading and storing to happen.
2024-05-11 02:17:11 -07:00
David Rubin
9229321400 riscv: change up how we do args
- before we were storing each arg in it's own function arg register. with this commit now we store the args in the fa register before calling as per the RISC-V calling convention, however as soon as we enter the callee, aka in airArg, we spill the argument to the stack. this allows us to spend less effort worrying about whether we're going to clobber the function arguments when another function is called inside of the callee.

- we were actually clobbering the fa regs inside of resolveCallingConvetion, because of the null argument to allocReg. now each lock is stored in an array which is then iterated over and unlocked, which actually aids in the first point of this commit.
2024-05-11 02:17:11 -07:00
David Rubin
5e010b6dea riscv: reorganize binOp and implement cmp_imm_gte MIR
this was an annoying one to do, as there is no (to my knowledge) myriad sequence
that will allow us to do `gte` compares with an immediate without allocating a register.
RISC-V provides a single instruction to do compares, that being `lt`, and so you need to
use more than one for other variants, but in this case, i believe you need to allocate a register.
2024-05-11 02:17:11 -07:00
David Rubin
63bbf66553 riscv: remove an allocation from dwarf.zig 2024-05-11 02:17:11 -07:00
David Rubin
190e7d0239 riscv: update builtin names 2024-05-11 02:17:11 -07:00
David Rubin
2cbd8e1deb riscv: progress toward arrays
- implement `airArrayElemVal` for arrays on the stack. This is really easy
as we can just move the offset by the bytes into the array. This only works
when the index access is comptime-known though, this won't work for runtime access.
2024-05-11 02:17:11 -07:00
David Rubin
9b2a4582c9 riscv: implement 64 bit immediate into register loading
LLVM has a better myriad sequence for this, where they don't allocate
a temporary register, but for now this will do.
2024-05-11 02:17:11 -07:00
David Rubin
f67fa73fe8 riscv: 16 bit @byteSwap 2024-05-11 02:17:11 -07:00
David Rubin
b2150094ba riscv: implement basic logical shifting 2024-05-11 02:17:11 -07:00
David Rubin
664e3e16fa riscv: add cmp_eq MIR instruction
this opens up the door for addition!
2024-05-11 02:17:11 -07:00
David Rubin
3ccf0fd4c2 riscv: basic struct field access
the current implementation only works when the struct is in a register. we use some shifting magic
to get the field into the LSB, and from there, given the type provenance, the generated code should
never reach into the bits beyond the bit size of the type and interact with the rest of the struct.
2024-05-11 02:17:11 -07:00
David Rubin
2be3033acd riscv: implement basic branching
we use a code offset map in Emit.zig to pre-compute what byte offset each MIR instruction is at. this is important because they can be
of different size
2024-05-11 02:17:11 -07:00
David Rubin
28df64cba4 riscv: implement @abs
- add the `abs` MIR instruction
- implement `@abs` by shifting to the right by `bits - 1`, and xoring.
2024-05-11 02:17:11 -07:00
David Rubin
060c475fcd riscv: update start.zig and restore ra from the proper stack offset 2024-05-11 02:17:11 -07:00
David Rubin
5e770407cf riscv: basic function arguments
- rename setRegOrMem -> setValue
- a naive method of passing arguments by register
- gather the prologue and epilogue and generate them in Emit.zig. this is cleaner because we have the final stack size in the emit step.
- define the "fa" register set, which contains the RISC-V calling convention defined function argument registers
2024-05-11 02:17:11 -07:00
David Rubin
dceff2592f riscv: initial cleanup and work 2024-05-11 02:17:11 -07:00
Dominic
1550b5b16d
astgen: fix result info for catch switch_block_err_union 2024-05-11 12:06:13 +03:00
190n
cc39ce28a1
Do not run asserts for WASI alignment when not targeting WASI 2024-05-11 07:23:07 +00:00
Andrew Kelley
6ca4ed5948 Revert "Merge pull request #19349 from nolanderc/save-commit"
This reverts commit 7fa2357d0586cef742bf691d69a6cffdd353b496, reversing
changes made to cb77bd672c3b398e3c5f6be80af03243bf8638e3.
2024-05-10 16:41:15 -07:00
Andrew Kelley
7fa2357d05
Merge pull request #19349 from nolanderc/save-commit
`zig fetch`: resolve branch/tag names to commit SHA
2024-05-10 16:27:30 -07:00
Pyrolistical
cb77bd672c [docs] add examples of array/slice init using result location 2024-05-10 13:56:01 -07:00
Lucas Santos
f71f27bcb0 Avoid unnecessary operation in PageAllocator.
There's no need to call `alignForward` before `VirtualAlloc`.
From [MSDN](https://learn.microsoft.com/en-us/windows/win32/api/memoryapi/nf-memoryapi-virtualalloc):
```
If the lpAddress parameter is NULL, this value is rounded up to the next page boundary
```
2024-05-10 22:51:52 +03:00
Abhinav Gupta
fe1b397606
ChildProcess: document StdIo behaviors (#17553)
Add some basic documentation for the different ChildProcess.StdIo
behaviors and the fields they affect.
2024-05-10 14:05:20 +00:00
expikr
841bb0a1fd
std.os.windows: add compileError warning against TCHAR & their corresponding string/pointer types (#18741) 2024-05-10 07:48:05 +00:00
Veikka Tuominen
c4e3a49898 define an error set for std.io.tty.Config.setColor 2024-05-10 10:29:16 +03:00
Garfield Lee
e69caaa39f
lib/std/os/windows/kernel32: add signature for SetConsoleMode (#18715)
- From lib/libc/include/any-windows-any/wincon.h#L235
- See also https://learn.microsoft.com/en-us/windows/console/setconsolemode
- Also add DISABLE_NEWLINE_AUTO_RETURN constant which will be used by SetConsoleMode in lib/std/os/windows.

Co-authored-by: Kexy Biscuit <kexybiscuit@biscuitt.in>
2024-05-09 16:38:39 -07:00
Pyry Kovanen
4163126c01 llvm: always include debug information for global variables 2024-05-09 16:02:03 -07:00
Karl Bohlmark
6eb17a034a fix integer overflow in IoUring buffer ring size calculation 2024-05-09 16:00:01 -07:00
Pavel Verigo
d4d1efeb3e std.compress.flate: fix panic when reading into empty buffer 2024-05-09 15:51:42 -07:00
Andrew Kelley
68629fedef
Merge pull request #19918 from ziglang/xros
Add support for VisionOS
2024-05-09 15:45:42 -07:00
february cozzocrea
c9ad1b5199 aro translate-c: support for record types added 2024-05-09 13:46:50 -07:00
Jakub Konka
47e840a9b9 test/llvm_targets: add watchos, tvos and visionos to test matrix 2024-05-09 22:19:45 +02:00
Jakub Konka
d3ba541034 codegen/llvm: handle missing Apple targets 2024-05-09 22:00:17 +02:00
Jakub Konka
39adc228d8 link/macho: look in lib dirs (-L) for libSystem too 2024-05-09 16:20:18 +02:00
Jakub Konka
2e1fc0dd14 handle visionos target OS tag in the compiler
* rename .xros to .visionos as agreed in the tracking issue
* add support for VisionOS platform in the MachO linker
2024-05-09 15:04:15 +02:00
Jakub Konka
8f202ba7c7 link/macho: add support for VisionOS 2024-05-09 14:09:31 +02:00
Andrew Kelley
bcb534c295 Merge branch 'llvm18'
Upgrades the LLVM, Clang, and LLD dependencies to LLVM 18.x

Related to #16270
2024-05-09 01:52:26 -07:00