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riscv: implement a basic @intCast
the truncation panic logic is generated in Sema, so I don't need to roll anything of my own. I add all of the boilerplate for that detecting the truncation and it works in basic test cases!
This commit is contained in:
David Rubin
parent
685f828218
commit
3c0015c828
@ -10499,9 +10499,10 @@ fn intCast(
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const dest_max_val_scalar = try dest_scalar_ty.maxIntScalar(mod, operand_scalar_ty);
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const dest_max_val = try sema.splat(operand_ty, dest_max_val_scalar);
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const dest_max = Air.internedToRef(dest_max_val.toIntern());
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const diff = try block.addBinOp(.sub_wrap, dest_max, operand);
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if (actual_info.signedness == .signed) {
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const diff = try block.addBinOp(.sub_wrap, dest_max, operand);
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// Reinterpret the sign-bit as part of the value. This will make
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// negative differences (`operand` > `dest_max`) appear too big.
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const unsigned_scalar_operand_ty = try mod.intType(.unsigned, actual_bits);
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@ -10542,7 +10543,7 @@ fn intCast(
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try sema.addSafetyCheck(block, src, ok, .cast_truncated_data);
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} else {
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const ok = if (is_vector) ok: {
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const is_in_range = try block.addCmpVector(diff, dest_max, .lte);
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const is_in_range = try block.addCmpVector(operand, dest_max, .lte);
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const all_in_range = try block.addInst(.{
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.tag = if (block.float_mode == .optimized) .reduce_optimized else .reduce,
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.data = .{ .reduce = .{
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@ -10552,7 +10553,7 @@ fn intCast(
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});
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break :ok all_in_range;
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} else ok: {
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const is_in_range = try block.addBinOp(.cmp_lte, diff, dest_max);
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const is_in_range = try block.addBinOp(.cmp_lte, operand, dest_max);
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break :ok is_in_range;
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};
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try sema.addSafetyCheck(block, src, ok, .cast_truncated_data);
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@ -797,23 +797,57 @@ fn airFpext(self: *Self, inst: Air.Inst.Index) !void {
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}
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fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {
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const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;
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if (self.liveness.isUnused(inst))
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return self.finishAir(inst, .dead, .{ ty_op.operand, .none, .none });
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const mod = self.bin_file.comp.module.?;
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const operand_ty = self.typeOf(ty_op.operand);
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const operand = try self.resolveInst(ty_op.operand);
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const info_a = operand_ty.intInfo(mod);
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const info_b = self.typeOfIndex(inst).intInfo(mod);
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if (info_a.signedness != info_b.signedness)
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return self.fail("TODO gen intcast sign safety in semantic analysis", .{});
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const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;
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const src_ty = self.typeOf(ty_op.operand);
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const dst_ty = self.typeOfIndex(inst);
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if (info_a.bits == info_b.bits)
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return self.finishAir(inst, operand, .{ ty_op.operand, .none, .none });
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const result: MCValue = result: {
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const dst_abi_size: u32 = @intCast(dst_ty.abiSize(mod));
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return self.fail("TODO implement intCast for {}", .{self.target.cpu.arch});
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// return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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const src_int_info = src_ty.intInfo(mod);
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const dst_int_info = dst_ty.intInfo(mod);
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const extend = switch (src_int_info.signedness) {
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.signed => dst_int_info,
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.unsigned => src_int_info,
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}.signedness;
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_ = dst_abi_size;
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_ = extend;
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const min_ty = if (dst_int_info.bits < src_int_info.bits) dst_ty else src_ty;
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const src_mcv = try self.resolveInst(ty_op.operand);
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const src_storage_bits: u16 = switch (src_mcv) {
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.register => 64,
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.stack_offset => src_int_info.bits,
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else => return self.fail("airIntCast from {s}", .{@tagName(src_mcv)}),
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};
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const dst_mcv = if (dst_int_info.bits <= src_storage_bits and
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math.divCeil(u16, dst_int_info.bits, 64) catch unreachable ==
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math.divCeil(u32, src_storage_bits, 64) catch unreachable and
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self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) src_mcv else dst: {
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const dst_mcv = try self.allocRegOrMem(inst, true);
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try self.setValue(min_ty, dst_mcv, src_mcv);
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break :dst dst_mcv;
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};
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if (dst_int_info.bits <= src_int_info.bits) {
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break :result dst_mcv;
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}
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if (dst_int_info.bits > 64 or src_int_info.bits > 64) {
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break :result null; // TODO
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}
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break :result dst_mcv;
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} orelse return self.fail("TODO implement airIntCast from {} to {}", .{
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src_ty.fmt(mod), dst_ty.fmt(mod),
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});
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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fn airTrunc(self: *Self, inst: Air.Inst.Index) !void {
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@ -1080,7 +1114,9 @@ fn binOpImm(
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.shr => .srli,
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.cmp_gte => .cmp_imm_gte,
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.cmp_eq => .cmp_imm_eq,
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.cmp_lte => .cmp_imm_lte,
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.add => .addi,
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.sub => .addiw,
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else => return self.fail("TODO: binOpImm {s}", .{@tagName(tag)}),
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};
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@ -1090,6 +1126,7 @@ fn binOpImm(
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.srli,
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.addi,
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.cmp_imm_eq,
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.cmp_imm_lte,
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=> {
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_ = try self.addInst(.{
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.tag = mir_tag,
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@ -1102,6 +1139,18 @@ fn binOpImm(
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} },
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});
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},
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.addiw => {
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_ = try self.addInst(.{
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.tag = mir_tag,
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.data = .{ .i_type = .{
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.rd = dest_reg,
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.rs1 = lhs_reg,
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.imm12 = -(math.cast(i12, rhs.immediate) orelse {
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return self.fail("TODO: binOpImm larger than i12 i_type payload", .{});
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}),
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} },
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});
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},
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.cmp_imm_gte => {
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const imm_reg = try self.copyToTmpRegister(rhs_ty, .{ .immediate = rhs.immediate - 1 });
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@ -1146,7 +1195,16 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
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fn airSubWrap(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[@intFromEnum(inst)].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else return self.fail("TODO implement subwrap for {}", .{self.target.cpu.arch});
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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// RISCV arthemtic instructions already wrap, so this is simply a sub binOp with
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// no overflow checks.
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.typeOf(bin_op.lhs);
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const rhs_ty = self.typeOf(bin_op.rhs);
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break :result try self.binOp(.sub, inst, lhs, rhs, lhs_ty, rhs_ty);
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -3441,3 +3499,7 @@ fn typeOfIndex(self: *Self, inst: Air.Inst.Index) Type {
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const mod = self.bin_file.comp.module.?;
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return self.air.typeOfIndex(inst, &mod.intern_pool);
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}
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fn hasFeature(self: *Self, feature: Target.riscv.Feature) bool {
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return Target.riscv.featureSetHas(self.target.cpu.features, feature);
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}
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@ -64,11 +64,13 @@ pub fn emitMir(
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.cmp_lt => try emit.mirRType(inst),
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.cmp_imm_gte => try emit.mirRType(inst),
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.cmp_imm_eq => try emit.mirIType(inst),
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.cmp_imm_lte => try emit.mirIType(inst),
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.beq => try emit.mirBType(inst),
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.bne => try emit.mirBType(inst),
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.addi => try emit.mirIType(inst),
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.addiw => try emit.mirIType(inst),
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.andi => try emit.mirIType(inst),
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.jalr => try emit.mirIType(inst),
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.abs => try emit.mirIType(inst),
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@ -259,6 +261,7 @@ fn mirIType(emit: *Emit, inst: Mir.Inst.Index) !void {
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switch (tag) {
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.addi => try emit.writeInstruction(Instruction.addi(rd, rs1, imm12)),
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.addiw => try emit.writeInstruction(Instruction.addiw(rd, rs1, imm12)),
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.jalr => try emit.writeInstruction(Instruction.jalr(rd, imm12, rs1)),
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.andi => try emit.writeInstruction(Instruction.andi(rd, rs1, imm12)),
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@ -288,6 +291,11 @@ fn mirIType(emit: *Emit, inst: Mir.Inst.Index) !void {
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try emit.writeInstruction(Instruction.xori(rd, rs1, imm12));
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try emit.writeInstruction(Instruction.sltiu(rd, rd, 1));
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},
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.cmp_imm_lte => {
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try emit.writeInstruction(Instruction.sltiu(rd, rs1, @bitCast(imm12)));
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},
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else => unreachable,
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}
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}
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@ -25,6 +25,7 @@ pub const Inst = struct {
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pub const Tag = enum(u16) {
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addi,
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addiw,
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jalr,
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lui,
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mv,
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@ -83,6 +84,8 @@ pub const Inst = struct {
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/// Immediate `==`, uses i_type
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cmp_imm_eq,
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/// Immediate `<=`, uses i_typei
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cmp_imm_lte,
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/// Branch if equal, Uses b_type
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beq,
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