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riscv: update start.zig and restore ra from the proper stack offset

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This commit is contained in:
David Rubin 2024-03-13 19:26:10 -07:00
parent 5e770407cf
commit 060c475fcd
2 changed files with 2 additions and 2 deletions
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2
lib/std/start.zig
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@ -155,7 +155,7 @@ fn exit2(code: usize) noreturn {
asm volatile ("ecall"
:
: [number] "{a7}" (94),
[arg1] "{a0}" (0),
[arg1] "{a0}" (code),
: "rcx", "r11", "memory"
);
},

2
src/arch/riscv64/Emit.zig
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@ -287,7 +287,7 @@ fn mirPsuedo(emit: *Emit, inst: Mir.Inst.Index) !void {
};
// Restore ra
try emit.writeInstruction(Instruction.ld(.ra, stack_size - 16, .sp));
try emit.writeInstruction(Instruction.ld(.ra, stack_size - 8, .sp));
// Restore s0
try emit.writeInstruction(Instruction.ld(.s0, stack_size - 16, .sp));