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riscv: add allocReg helper, and clean up some comparing logic
- Added the basic framework for panicing with an overflow in `airAddWithOverflow`, but there is no check done yet. - added the `cmp_lt`, `cmp_gte`, and `cmp_imm_eq` MIR instructions, and their respective functionality.
This commit is contained in:
David Rubin
parent
08452b1add
commit
09b7aabe09
@ -736,6 +736,15 @@ fn allocRegOrMem(self: *Self, inst: Air.Inst.Index, reg_ok: bool) !MCValue {
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return MCValue{ .stack_offset = stack_offset };
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}
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/// Allocates a register from the general purpose set and returns the Register and the Lock.
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///
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/// Up to the user to unlock the register later.
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fn allocReg(self: *Self) !struct { Register, RegisterLock } {
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const reg = try self.register_manager.allocReg(null, gp);
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const lock = self.register_manager.lockRegAssumeUnused(reg);
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return .{ reg, lock };
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}
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pub fn spillInstruction(self: *Self, reg: Register, inst: Air.Inst.Index) !void {
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const stack_mcv = try self.allocRegOrMem(inst, false);
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log.debug("spilling {d} to stack mcv {any}", .{ inst, stack_mcv });
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@ -983,67 +992,36 @@ fn binOpRegister(
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lhs_ty: Type,
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rhs_ty: Type,
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) !MCValue {
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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_ = maybe_inst;
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const lhs_lock: ?RegisterLock = if (lhs_is_register)
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self.register_manager.lockReg(lhs.register)
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else
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null;
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defer if (lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const lhs_reg, const lhs_lock = blk: {
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if (lhs == .register) break :blk .{ lhs.register, null };
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[@intFromEnum(inst)].bin_op;
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break :inst bin_op.lhs.toIndex().?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst, gp);
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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const lhs_reg, const lhs_lock = try self.allocReg();
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try self.genSetReg(lhs_ty, lhs_reg, lhs);
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break :blk .{ lhs_reg, lhs_lock };
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};
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const new_lhs_lock = self.register_manager.lockReg(lhs_reg);
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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const rhs_reg = if (rhs_is_register) rhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[@intFromEnum(inst)].bin_op;
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break :inst bin_op.rhs.toIndex().?;
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} else null;
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const rhs_reg, const rhs_lock = blk: {
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if (rhs == .register) break :blk .{ rhs.register, null };
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const reg = try self.register_manager.allocReg(track_inst, gp);
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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const rhs_reg, const rhs_lock = try self.allocReg();
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try self.genSetReg(rhs_ty, rhs_reg, rhs);
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break :blk .{ rhs_reg, rhs_lock };
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};
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const new_rhs_lock = self.register_manager.lockReg(rhs_reg);
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defer if (new_rhs_lock) |reg| self.register_manager.unlockReg(reg);
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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const dest_reg = if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[@intFromEnum(inst)].bin_op;
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if (lhs_is_register and self.reuseOperand(inst, bin_op.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else if (rhs_is_register and self.reuseOperand(inst, bin_op.rhs, 1, rhs)) {
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break :blk rhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst, gp);
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}
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} else try self.register_manager.allocReg(null, gp);
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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const dest_reg, const dest_lock = try self.allocReg();
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defer self.register_manager.unlockReg(dest_lock);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add,
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.sub => .sub,
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.cmp_eq => .cmp_eq,
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.cmp_gt => .cmp_gt,
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.cmp_gte => .cmp_gte,
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.cmp_lt => .cmp_lt,
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.shl => .sllw,
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.shr => .srlw,
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else => return self.fail("TODO: binOpRegister {s}", .{@tagName(tag)}),
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@ -1080,48 +1058,28 @@ fn binOpImm(
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rhs_ty: Type,
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) !MCValue {
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assert(rhs == .immediate);
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_ = maybe_inst;
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const lhs_is_register = lhs == .register;
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// TODO: use `maybe_inst` to track instead of forcing a lock.
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const lhs_lock: ?RegisterLock = if (lhs_is_register)
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self.register_manager.lockReg(lhs.register)
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else
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null;
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defer if (lhs_lock) |reg| self.register_manager.unlockReg(reg);
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const lhs_reg, const lhs_lock = blk: {
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if (lhs == .register) break :blk .{ lhs.register, null };
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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const lhs_reg = if (lhs_is_register) lhs.register else blk: {
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const track_inst: ?Air.Inst.Index = if (maybe_inst) |inst| inst: {
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const bin_op = self.air.instructions.items(.data)[@intFromEnum(inst)].bin_op;
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break :inst bin_op.lhs.toIndex().?;
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} else null;
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const reg = try self.register_manager.allocReg(track_inst, gp);
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if (track_inst) |inst| branch.inst_table.putAssumeCapacity(inst, .{ .register = reg });
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break :blk reg;
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const lhs_reg, const lhs_lock = try self.allocReg();
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try self.genSetReg(lhs_ty, lhs_reg, lhs);
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break :blk .{ lhs_reg, lhs_lock };
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};
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const new_lhs_lock = self.register_manager.lockReg(lhs_reg);
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defer if (new_lhs_lock) |reg| self.register_manager.unlockReg(reg);
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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const dest_reg = if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[@intFromEnum(inst)].bin_op;
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if (lhs_is_register and self.reuseOperand(inst, bin_op.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst, gp);
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}
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} else try self.register_manager.allocReg(null, gp);
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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const dest_reg, const dest_lock = try self.allocReg();
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defer self.register_manager.unlockReg(dest_lock);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.shl => .slli,
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.shr => .srli,
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.cmp_gte => .cmp_imm_gte,
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.cmp_eq => .cmp_imm_eq,
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.add => .addi,
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else => return self.fail("TODO: binOpImm {s}", .{@tagName(tag)}),
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};
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@ -1129,6 +1087,8 @@ fn binOpImm(
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switch (mir_tag) {
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.slli,
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.srli,
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.addi,
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.cmp_imm_eq,
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=> {
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_ = try self.addInst(.{
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.tag = mir_tag,
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@ -1156,8 +1116,6 @@ fn binOpImm(
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else => unreachable,
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}
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// generate the struct for overflow checks
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return MCValue{ .register = dest_reg };
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}
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@ -1216,6 +1174,7 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void {
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}
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fn airAddWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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const mod = self.bin_file.comp.module.?;
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const ty_pl = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_pl;
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const extra = self.air.extraData(Air.Bin, ty_pl.payload).data;
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@ -1225,7 +1184,28 @@ fn airAddWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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const lhs_ty = self.typeOf(extra.lhs);
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const rhs_ty = self.typeOf(extra.rhs);
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break :result try self.binOp(.add, null, lhs, rhs, lhs_ty, rhs_ty);
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const partial_mcv = try self.binOp(.add, null, lhs, rhs, lhs_ty, rhs_ty);
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const tuple_ty = self.typeOfIndex(inst);
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// TODO: optimization, set this to true. needs the other struct access stuff to support
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// accessing registers.
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const result_mcv = try self.allocRegOrMem(inst, false);
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const offset = result_mcv.stack_offset;
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const overflow_offset = tuple_ty.structFieldOffset(1, mod) + offset;
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const result_offset = tuple_ty.structFieldOffset(0, mod) + offset;
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const overflow_mcv = try self.binOp(.cmp_lt, null, partial_mcv, lhs, lhs_ty, lhs_ty);
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const overflow_reg, const overflow_lock = try self.allocReg();
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defer self.register_manager.unlockReg(overflow_lock);
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try self.genSetReg(lhs_ty, overflow_reg, overflow_mcv);
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try self.genSetStack(Type.u1, @intCast(overflow_offset), overflow_mcv);
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try self.genSetStack(lhs_ty, @intCast(result_offset), partial_mcv);
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break :result result_mcv;
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};
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return self.finishAir(inst, result, .{ extra.lhs, extra.rhs, .none });
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@ -1749,6 +1729,15 @@ fn store(self: *Self, pointer: MCValue, value: MCValue, ptr_ty: Type, value_ty:
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.dead => unreachable,
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.ptr_stack_offset => |off| try self.genSetStack(value_ty, off, value),
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.stack_offset => {
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const pointer_reg, const lock = try self.allocReg();
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defer self.register_manager.unlockReg(lock);
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try self.genSetReg(ptr_ty, pointer_reg, pointer);
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return self.store(.{ .register = pointer_reg }, value, ptr_ty, value_ty);
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},
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.register => |reg| {
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const value_reg = try self.copyToTmpRegister(value_ty, value);
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@ -2165,7 +2154,7 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
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const cond_reg_lock = self.register_manager.lockRegAssumeUnused(cond_reg);
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defer self.register_manager.unlockReg(cond_reg_lock);
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// A branch to the false section. Uses bne
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// A branch to the false section. Uses beq. 1 is the default "true" state.
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const reloc = try self.condBr(cond_ty, cond, cond_reg);
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// If the condition dies here in this condbr instruction, process
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@ -2301,7 +2290,7 @@ fn condBr(self: *Self, cond_ty: Type, condition: MCValue, cond_reg: Register) !M
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try self.genSetReg(cond_ty, cond_reg, condition);
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return try self.addInst(.{
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.tag = .bne,
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.tag = .beq,
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.data = .{
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.b_type = .{
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.rs1 = cond_reg,
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@ -2729,8 +2718,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, src_val: MCValue) Inner
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=> {
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// TODO: remove this lock in favor of a copyToTmpRegister when we load 64 bit immediates with
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// a register allocation.
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const reg = try self.register_manager.allocReg(null, gp);
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const reg_lock = self.register_manager.lockRegAssumeUnused(reg);
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const reg, const reg_lock = try self.allocReg();
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defer self.register_manager.unlockReg(reg_lock);
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try self.genSetReg(ty, reg, src_val);
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@ -2939,8 +2927,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_val: MCValue) InnerError!
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// TODO: use a more advanced myriad seq to do this without a reg.
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// see: https://github.com/llvm/llvm-project/blob/081a66ffacfe85a37ff775addafcf3371e967328/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp#L224
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const temp = try self.register_manager.allocReg(null, gp);
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const temp_lock = self.register_manager.lockRegAssumeUnused(temp);
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const temp, const temp_lock = try self.allocReg();
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defer self.register_manager.unlockReg(temp_lock);
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const lo32: i32 = @truncate(x);
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@ -59,7 +59,10 @@ pub fn emitMir(
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.cmp_eq => try emit.mirRType(inst),
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.cmp_gt => try emit.mirRType(inst),
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.cmp_gte => try emit.mirRType(inst),
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.cmp_lt => try emit.mirRType(inst),
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.cmp_imm_gte => try emit.mirRType(inst),
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.cmp_imm_eq => try emit.mirIType(inst),
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.beq => try emit.mirBType(inst),
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.bne => try emit.mirBType(inst),
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@ -188,7 +191,12 @@ fn mirRType(emit: *Emit, inst: Mir.Inst.Index) !void {
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.sub => try emit.writeInstruction(Instruction.sub(rd, rs1, rs2)),
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.cmp_gt => {
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// rs1 > rs2
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try emit.writeInstruction(Instruction.slt(rd, rs1, rs2));
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try emit.writeInstruction(Instruction.sltu(rd, rs2, rs1));
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},
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.cmp_gte => {
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// rs1 >= rs2
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try emit.writeInstruction(Instruction.sltu(rd, rs1, rs2));
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try emit.writeInstruction(Instruction.xori(rd, rd, 1));
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},
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.cmp_eq => {
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// rs1 == rs2
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@ -198,14 +206,19 @@ fn mirRType(emit: *Emit, inst: Mir.Inst.Index) !void {
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// if rd == 0, set rd to 1
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try emit.writeInstruction(Instruction.sltiu(rd, rd, 1));
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},
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.cmp_lt => {
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// rd = 1 if rs1 < rs2
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try emit.writeInstruction(Instruction.slt(rd, rs1, rs2));
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},
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.sllw => try emit.writeInstruction(Instruction.sllw(rd, rs1, rs2)),
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.srlw => try emit.writeInstruction(Instruction.srlw(rd, rs1, rs2)),
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.@"or" => try emit.writeInstruction(Instruction.@"or"(rd, rs1, rs2)),
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.cmp_imm_gte => {
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// rd = rs1 >= imm12
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// see the docstring for cmp_imm_gte to see why we use r_type here
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try emit.writeInstruction(Instruction.slt(rd, rs1, rs2));
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try emit.writeInstruction(Instruction.xori(rd, rd, 1));
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// rd = 1 if rs1 >= imm12
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// see the docstring of cmp_imm_gte to see why we use r_type here
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// (rs1 >= imm12) == !(imm12 > rs1)
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try emit.writeInstruction(Instruction.sltu(rd, rs1, rs2));
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},
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else => unreachable,
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}
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@ -263,6 +276,10 @@ fn mirIType(emit: *Emit, inst: Mir.Inst.Index) !void {
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.srli => try emit.writeInstruction(Instruction.srli(rd, rs1, @intCast(imm12))),
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.slli => try emit.writeInstruction(Instruction.slli(rd, rs1, @intCast(imm12))),
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.cmp_imm_eq => {
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try emit.writeInstruction(Instruction.xori(rd, rs1, imm12));
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try emit.writeInstruction(Instruction.sltiu(rd, rd, 1));
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},
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else => unreachable,
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}
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}
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@ -490,13 +507,17 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
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.dbg_prologue_end,
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=> 0,
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.psuedo_epilogue => 12,
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.psuedo_prologue => 16,
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.psuedo_prologue,
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=> 16,
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.abs => 12,
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.psuedo_epilogue,
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.abs,
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=> 12,
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.cmp_eq => 8,
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.cmp_imm_gte => 8,
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.cmp_eq,
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.cmp_imm_eq,
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.cmp_gte,
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=> 8,
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else => 4,
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};
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@ -62,6 +62,10 @@ pub const Inst = struct {
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cmp_eq,
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/// Register `>`, uses r_type
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cmp_gt,
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/// Register `<`, uses r_type
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cmp_lt,
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/// Register `>=`, uses r_type
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cmp_gte,
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/// Immediate `>=`, uses r_type
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///
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@ -72,6 +76,9 @@ pub const Inst = struct {
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/// allocate a register for temporary use.
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cmp_imm_gte,
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/// Immediate `==`, uses i_type
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cmp_imm_eq,
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/// Branch if equal, Uses b_type
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beq,
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/// Branch if not equal, Uses b_type
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