16280 Commits

Author SHA1 Message Date
Jakub Konka
e7ac05e882 stage2: rename Emit to Isel for x86_64 2021-12-31 11:18:23 +01:00
Jarred Sumner
2d9508780a For unused references & redundant keywords, append the compiler error but continue running AstGen 2021-12-30 22:45:43 -05:00
Andrew Kelley
4645ec89f7
Merge pull request #10455 from joachimschmidt557/stage2-arm
stage2 ARM: basic slice + basic struct support
2021-12-30 15:25:36 -05:00
drew
2f53406ad8
CBE; implement airLoad and airStore for arrays (#10452)
Effectively a small continuation of #10152

This allows the for.zig behavior tests to pass. Unfortunately to fully test everything I had to move a lot of behavior tests from array.zig; most of them now pass (sorry @rainbowbismuth!)

I'm also conflicted on how I store constants into arrays because it's kind of stupid; array's can't be re-initialized using the same syntax, so instead of initializing each element, a new array is made which is copied into the destination. This also required that renderValue can't emit string literals for byte arrays given that they need to always have an extra byte for the NULL terminator, meaning that strings are no longer grep-able in the output.
2021-12-30 15:19:12 -05:00
joachimschmidt557
726ee671be stage2 x86_64: add regression test for #7187 2021-12-30 15:12:38 -05:00
joachimschmidt557
69d03d3a29
stage2 ARM: implement struct_field_ptr and struct_field_val 2021-12-30 14:39:06 +01:00
joachimschmidt557
ac7fa95af4
stage2 ARM: add genArmInlineMemcpy for copying types with size > 4 2021-12-30 14:24:03 +01:00
Andrew Kelley
06286b05a4
Merge pull request #10446 from ziglang/stage2-x86_64-mov-mem-imm
stage2: more fixes to x86_64 codegen, mir and isel
2021-12-29 22:22:26 -05:00
Jakub Konka
4ecc5956f6 stage2: update PrintMir with latest instructions and Isel changes 2021-12-29 22:06:38 +01:00
Jakub Konka
b7e2235973 stage2: lower 1-byte and 2-byte values saved to stack
* fix handling of `ah`, `bh`, `ch`, and `dh` registers (which are
  actually used as aliases to `dil`, etc. registers). Currenly, we
  treat them as aliases only meaning when we encounter `ah` we make
  sure to set the REX.W to promote the instruction to 64bits and use
  `dil` register instead - otherwise we might have mismatch between
  registers used in different parts of the codegen. In the future,
  we can and should use `ah`, etc. as upper 8bit halves of 16bit
  registers `ax`, etc.
* fix bug in `airCmp` where `.cmp` MIR instruction shouldn't force
  type `Bool` but let the type of the original type propagate downwards
  - we need this to make an informed choice of the target register
  size and hence choose the right encoding down the line.
* implement lowering of 1-byte and 2-byte values to stack and add
  matching stage2 tests for x86_64 codegen
2021-12-29 22:06:38 +01:00
Jakub Konka
08ea1a2eab stage2: add separate tag for MI encoding
To request memory-immediate encoding at the MIR side, we should now
use a new tag such as `mov_mem_imm` where the size of the memory
pointer is encoded as the flags:

```
0b00 => .byte_ptr,
0b01 => .word_ptr,
0b10 => .dword_ptr,
0b11 => .qword_ptr,
```
2021-12-29 22:06:38 +01:00
joachimschmidt557
baec07cfcd
stage2 ARM: change MCValue.immediate to u32 2021-12-29 11:27:37 +01:00
joachimschmidt557
96e59fd1c2
stage2 ARM: implement slice_elem_val for sizes > 4 2021-12-29 11:08:48 +01:00
Andrew Kelley
be5130ec53 compiler_rt: move more functions to the stage2 section
also move more already-passing behavior tests to the passing section.
2021-12-29 00:39:25 -07:00
Andrew Kelley
efb7148a45 Sema: more union fixes
* `Module.Union.getLayout`: fixes to support components of the union
   being 0 bits.
 * Implement `@typeInfo` for unions.
 * Add missing calls to `resolveTypeFields`.
 * Fix explicitly-provided union tag types passing a `Zir.Inst.Ref`
   where an `Air.Inst.Ref` was expected. We don't have any type safety
   for this; these typess are aliases.
 * Fix explicitly-provided `union(enum)` tag Values allocated to the
   wrong arena.
2021-12-28 23:22:09 -07:00
Andrew Kelley
91619cdf57 Sema: implement calling a fn ptr via a union field
Also, ignore `packed` on unions because that will be removed from the
language.
2021-12-28 23:22:09 -07:00
Tom Manner
2dd7255713 Fixed typo in deprecation error for E format specifier where it would instead complain about a specifier of X. 2021-12-29 01:02:04 -05:00
Andrew Kelley
81a3910e44 Sema: improve union support
* reduce number of branches in zirCmpEq
 * implement equality comparison for enums and unions
 * fix coercion from union to its tag type resulting in the wrong type
 * fix method calls of unions
 * implement peer type resolution for unions, enums, and enum literals
 * fix union tag type memory in the wrong arena
2021-12-28 20:20:30 -07:00
Andrew Kelley
6229d37dcf stage2: handle function dependency failures without crashing 2021-12-28 20:20:30 -07:00
joachimschmidt557
c0ae9647f9 stage2 ARM: implement slice_elem_val for types with size <= 4 2021-12-28 20:38:37 -05:00
Veikka Tuominen
4f4f0bc6f0 stage1: fix access of slice sentinel at comptime 2021-12-28 14:44:46 +02:00
Andrew Kelley
4b9b9e7257 stage2: LLVM backend: fix lowering of union constants
Comment from this commit reproduced here:

LLVM does not allow us to change the type of globals. So we must
create a new global with the correct type, copy all its attributes,
and then update all references to point to the new global,
delete the original, and rename the new one to the old one's name.
This is necessary because LLVM does not support const bitcasting
a struct with padding bytes, which is needed to lower a const union value
to LLVM, when a field other than the most-aligned is active. Instead,
we must lower to an unnamed struct, and pointer cast at usage sites
of the global. Such an unnamed struct is the cause of the global type
mismatch, because we don't have the LLVM type until the *value* is created,
whereas the global needs to be created based on the type alone, because
lowering the value may reference the global as a pointer.
2021-12-28 01:53:58 -07:00
Andrew Kelley
232f8a291d stage2: fix build on 32-bit targets
Regressed in 85d4c8620f602726b159efe1fe2ea0e07e3c5b59.
2021-12-28 01:15:36 -07:00
Andrew Kelley
85d4c8620f Sema: implement array coercion 2021-12-27 22:06:23 -07:00
Ali Chraghi
042b770d62
std: Skip comptime struct fields in mem.zeroes() (#10406)
closes #9934
2021-12-27 23:33:11 -05:00
Andrew Kelley
6ed7850972 Sema: fix anytype parameters whose types require comptime 2021-12-27 19:39:28 -07:00
Andrew Kelley
fc1a5cd9e7 Sema: implement @tagName for enum literals 2021-12-27 18:10:24 -07:00
Andrew Kelley
9dd4fb4130 stage2: fix 0-bit function parameters
Before this commit, Zig would incorrectly emit `arg` AIR instructions
for parameters whose types were 0-bit.
2021-12-27 17:56:33 -07:00
Andrew Kelley
886df772f0 stage2: LLVM backend: fix const packed structs
When doing LLVM const bit shifting we must make sure the integer bit
sizes are wide enough or else LLVM gives us a poison result.
2021-12-27 16:59:26 -07:00
Frank Denis
3abe464b06 crypto/edwards25519: faster point decompression
Make recovery of the x-coordinate slightly faster.

See https://mailarchive.ietf.org/arch/msg/cfrg/qlKpMBqxXZYmDpXXIx6LO3Oznv4/
for details.
2021-12-27 14:42:58 -08:00
Matthew Hall
4266795743 stage2: make tests/behaviour/void.zig work with c backend
* fix initialisation of void* fields of structs (initialises to 0xaa.. rather than {})
* don't generate struct fields when the field type does not have codegen bits
* in airAlloc generate a void* literal if the element type does not have codegen bits
2021-12-27 14:42:25 -08:00
Jan Philipp Hafer
17046674a7 compiler_rt: add __negvsi2, __negvdi2, __negvti2
- neg can only overflow, if a == MIN
- case `-0` is properly handled by hardware, so overflow check by comparing
  `a == MIN` is sufficient
- tests: MIN, MIN+1, MIN+4, -42, -7, -1, 0, 1, 7..

See #1290
2021-12-27 14:35:45 -08:00
Andrew Kelley
70894d5c2f AstGen: fix loop result locations
The main problem was that the loop body was treated as an expression
that was one of the peer result values of a loop, when in reality the
loop body is noreturn and only the `break` operands are the result
values of loops.

This was solved by introducing an override that prevents rvalue() from
emitting a store to result location instruction for loop bodies.

An orthogonal change also included in this commit is switching
`elem_val` index expressions to using `coerced_ty` and doing the
coercion to `usize` inside `Sema`, resulting in smaller ZIR (since the
cast becomes implied).

I also changed the break operand expression to use `reachableExpr`,
introducing a new compile error for double break.

This makes a few more behavior tests pass for `while` and `for` loops.
2021-12-27 15:30:31 -07:00
daurnimator
2c23699594
Bcrypt pbkdf (#10331)
* Make bcrypt State struct public

This is useful to implement the various protocols outside of the standard library

* Implement bcrypt pbkdf

This variant is used in e.g. SSH
The OpenBSD implementation was used as a reference
2021-12-27 21:59:32 +01:00
Andrew Kelley
c8fb36b36c stage2: LLVM backend: implement @tagName for enums
Introduced a new AIR instruction: `tag_name`. Reasons to do this
instead of lowering it in Sema to a switch, function call, array
lookup, or if-else tower:
 * Sema is a bottleneck; do less work in Sema whenever possible.
 * If any optimization passes run, and the operand to becomes
   comptime-known, then it could change to have a comptime result
   value instead of lowering to a function or array or something which
   would then have to be garbage-collected.
 * Backends may want to choose to use a function and a switch branch,
   or they may want to use a different strategy.

Codegen for `@tagName` is implemented for the LLVM backend but not any
others yet.

Introduced some new `Type` tags:
 * `const_slice_u8_sentinel_0`
 * `manyptr_const_u8_sentinel_0`

The motivation for this was to make typeof() on the tag_name AIR
instruction non-allocating.

A bunch more enum tests are passing now.
2021-12-27 01:14:50 -07:00
Andrew Kelley
f41b9cdb6d Sema: fix enum tag type not initialized when 0 fields 2021-12-26 21:36:12 -07:00
Andrew Kelley
629a54c711 Sema: improve non-exhaustive enum support
* remove false positive "all prongs handled" compile error for
   non-exhaustive enums.
 * implement `@TypeInfo` for enums, except enums which have any
   declarations is still TODO.
 * `getBuiltin` uses nomespaceLookup/analyzeDeclVal rather than
   namespaceLookupRef/analyzeLoad. Avoids a detour through an
   unnecessary type, and adds a detour through a caching mechanism.
 * `Value.eql`: add missing code to handle enum comparisons for
   non-exhaustive enums. It works by converting the enum tags to numeric
   values and comparing those.
2021-12-26 21:07:16 -07:00
Jan Philipp Hafer
405ff911da compiler_rt: add __absvsi2, __absvdi2, __absvti2
- abs can only overflow, if a == MIN
- comparing the sign change from wrapping addition is branchless
- tests: MIN, MIN+1,..MIN+4, -42, -7, -1, 0, 1, 7..

See #1290
2021-12-26 13:21:18 -08:00
Andrew Kelley
71923d7e40
Merge pull request #10414 from joachimschmidt557/stage2-arm
stage2 ARM: Implement airLoad for slices
2021-12-26 13:18:55 -08:00
joachimschmidt557
8a0e86cd5c
stage2 ARM: implement load for types with size 8 (e.g. slices) 2021-12-26 17:05:08 +01:00
joachimschmidt557
15f0f9240d
stage2 codegen: Implement generateSymbol for undefined values 2021-12-26 16:40:51 +01:00
Andrew Kelley
6b8e33d14c stage2: LLVM: fix lowering of packed structs
* ensure enough capacity when building the LLVM type and value.
 * add explicit padding field and populate it to ensure proper
   alignment.
2021-12-24 02:37:54 -07:00
Andrew Kelley
5b171f446f stage2: initial implementation of packed structs
Layout algorithm: all `align(0)` fields are squished together as if they
were a single integer with a number of bits equal to `@bitSizeOf` each
field added together. Then the natural ABI alignment of that integer is
used for that pseudo-field.
2021-12-23 23:57:02 -07:00
Andrew Kelley
3763580e1e add missing files to CMakeLists 2021-12-23 17:48:58 -07:00
Andrew Kelley
0049c7180f
Merge pull request #10394 from ziglang/stage2-x86_64-mir-intel-syntax
stage2: rewrite MIR -> Isel layer for x86_64
2021-12-23 16:39:51 -08:00
Andrew Kelley
4c11986650
MIR: remove unnecessary TODO comment
it wouldn't save any bytes in the MIR, and we can just check the range of the value when lowering the MIR to machine code.
2021-12-23 16:39:28 -08:00
Jakub Konka
35fe088e0e stage2: add lowering of RMI encoding
Example includes imul with 3 operands such as imul r64, r/m64, imm32.
2021-12-23 21:14:14 +01:00
Jakub Konka
dba5df64ea stage2: use lowerToRmEnc to lower two-operand imul
Fix mismatched register sizes in codegen.
2021-12-23 20:51:48 +01:00
Jakub Konka
c50bb2b80f stage2: lower jcc and setcc conditional jump/set instructions 2021-12-23 20:29:34 +01:00
Jakub Konka
8c664d3f6a stage2: support multibyte opcodes and refactor 1byte opcode changes 2021-12-23 18:49:40 +01:00