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Merge pull request #10446 from ziglang/stage2-x86_64-mov-mem-imm
stage2: more fixes to x86_64 codegen, mir and isel
This commit is contained in:
Andrew Kelley
GitHub
commit
06286b05a4
@ -329,7 +329,11 @@ pub fn generate(
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if (builtin.mode == .Debug and bin_file.options.module.?.comp.verbose_mir) {
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const w = std.io.getStdErr().writer();
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w.print("# Begin Function MIR: {s}:\n", .{module_fn.owner_decl.name}) catch {};
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const print = @import("./PrintMir.zig"){ .mir = mir };
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const PrintMir = @import("PrintMir.zig");
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const print = PrintMir{
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.mir = mir,
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.bin_file = bin_file,
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};
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print.printMir(w, function.mir_to_air_map, air) catch {}; // we don't care if the debug printing fails
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w.print("# End Function MIR: {s}\n\n", .{module_fn.owner_decl.name}) catch {};
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}
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@ -1642,11 +1646,11 @@ fn genBinMathOpMir(
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});
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},
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.immediate => |imm| {
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// TODO I am not quite sure why we need to set the size of the register here...
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const abi_size = dst_ty.abiSize(self.target.*);
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_ = try self.addInst(.{
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.tag = mir_tag,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(dst_reg, 4),
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.reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),
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}).encode(),
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.data = .{ .imm = @intCast(i32, imm) },
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});
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@ -1751,13 +1755,14 @@ fn genIMulOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !
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});
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},
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.immediate => |imm| {
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// TODO take into account the type's ABI size when selecting the register alias
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// register, immediate
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if (imm <= math.maxInt(i32)) {
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_ = try self.addInst(.{
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.tag = .imul_complex,
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.ops = (Mir.Ops{
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.reg1 = dst_reg,
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.reg2 = dst_reg,
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.reg1 = dst_reg.to32(),
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.reg2 = dst_reg.to32(),
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = @intCast(i32, imm) },
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@ -2147,7 +2152,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
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// This instruction supports only signed 32-bit immediates at most.
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const src_mcv = try self.limitImmediateType(bin_op.rhs, i32);
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try self.genBinMathOpMir(.cmp, Type.initTag(.bool), dst_mcv, src_mcv);
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try self.genBinMathOpMir(.cmp, ty, dst_mcv, src_mcv);
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break :result switch (ty.isSignedInt()) {
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true => MCValue{ .compare_flags_signed = op },
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false => MCValue{ .compare_flags_unsigned = op },
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@ -2792,25 +2797,24 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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return self.fail("TODO implement set stack variable with large stack offset", .{});
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}
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switch (abi_size) {
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1 => {
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return self.fail("TODO implement set abi_size=1 stack variable with immediate", .{});
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},
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2 => {
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return self.fail("TODO implement set abi_size=2 stack variable with immediate", .{});
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},
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4 => {
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1, 2, 4 => {
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// We have a positive stack offset value but we want a twos complement negative
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// offset from rbp, which is at the top of the stack frame.
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// mov DWORD PTR [rbp+offset], immediate
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// mov [rbp+offset], immediate
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const payload = try self.addExtra(Mir.ImmPair{
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.dest_off = -@intCast(i32, adj_off),
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.operand = @bitCast(i32, @intCast(u32, x_big)),
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});
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_ = try self.addInst(.{
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.tag = .mov,
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.tag = .mov_mem_imm,
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.ops = (Mir.Ops{
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.reg1 = .rbp,
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.flags = 0b11,
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.flags = switch (abi_size) {
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1 => 0b00,
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2 => 0b01,
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4 => 0b10,
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else => unreachable,
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},
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}).encode(),
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.data = .{ .payload = payload },
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});
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@ -2828,10 +2832,10 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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.operand = @bitCast(i32, @truncate(u32, x_big >> 32)),
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});
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_ = try self.addInst(.{
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.tag = .mov,
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.tag = .mov_mem_imm,
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.ops = (Mir.Ops{
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.reg1 = .rbp,
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.flags = 0b11,
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.flags = 0b10,
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}).encode(),
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.data = .{ .payload = payload },
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});
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@ -2842,10 +2846,10 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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.operand = @bitCast(i32, @truncate(u32, x_big)),
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});
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_ = try self.addInst(.{
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.tag = .mov,
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.tag = .mov_mem_imm,
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.ops = (Mir.Ops{
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.reg1 = .rbp,
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.flags = 0b11,
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.flags = 0b10,
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}).encode(),
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.data = .{ .payload = payload },
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});
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@ -2954,12 +2958,12 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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return;
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}
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if (x <= math.maxInt(i32)) {
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const abi_size = ty.abiSize(self.target.*);
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// Next best case: if we set the lower four bytes, the upper four will be zeroed.
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// TODO I am not quite sure why we need to set the size of the register here...
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, 4),
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.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
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}).encode(),
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.data = .{ .imm = @intCast(i32, x) },
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});
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@ -2985,9 +2989,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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// We need the offset from RIP in a signed i32 twos complement.
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const payload = try self.addExtra(Mir.Imm64.encode(code_offset));
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_ = try self.addInst(.{
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.tag = .lea_rip,
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = reg,
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.flags = 0b01,
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}).encode(),
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.data = .{ .payload = payload },
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});
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@ -3011,10 +3016,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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if (self.bin_file.options.pie) {
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// TODO we should flag up `x` as GOT symbol entry explicitly rather than as a hack.
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_ = try self.addInst(.{
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.tag = .lea_rip,
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = reg,
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.flags = 0b01,
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.flags = 0b10,
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}).encode(),
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.data = .{ .got_entry = @intCast(u32, x) },
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});
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File diff suppressed because it is too large
Load Diff
@ -38,13 +38,18 @@ pub const Inst = struct {
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/// 0b01 reg1, [reg2 + imm32]
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/// 0b01 reg1, [ds:imm32]
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/// 0b10 [reg1 + imm32], reg2
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/// 0b10 [reg1 + 0], imm32
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/// 0b11 [reg1 + imm32], imm32
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/// Notes:
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/// * If reg2 is `none` then it means Data field `imm` is used as the immediate.
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/// * When two imm32 values are required, Data field `payload` points at `ImmPair`.
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adc,
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/// ops flags: form:
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/// 0b00 byte ptr [reg1 + imm32], imm8
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/// 0b01 word ptr [reg1 + imm32], imm16
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/// 0b10 dword ptr [reg1 + imm32], imm32
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/// 0b11 qword ptr [reg1 + imm32], imm32 (sign-extended to imm64)
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adc_mem_imm,
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/// form: reg1, [reg2 + scale*rcx + imm32]
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/// ops flags scale
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/// 0b00 1
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@ -77,74 +82,95 @@ pub const Inst = struct {
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// The following instructions all have the same encoding as `adc`.
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add,
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add_mem_imm,
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add_scale_src,
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add_scale_dst,
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add_scale_imm,
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sub,
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sub_mem_imm,
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sub_scale_src,
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sub_scale_dst,
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sub_scale_imm,
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xor,
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xor_mem_imm,
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xor_scale_src,
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xor_scale_dst,
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xor_scale_imm,
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@"and",
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and_mem_imm,
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and_scale_src,
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and_scale_dst,
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and_scale_imm,
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@"or",
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or_mem_imm,
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or_scale_src,
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or_scale_dst,
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or_scale_imm,
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rol,
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rol_mem_imm,
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rol_scale_src,
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rol_scale_dst,
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rol_scale_imm,
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ror,
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ror_mem_imm,
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ror_scale_src,
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ror_scale_dst,
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ror_scale_imm,
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rcl,
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rcl_mem_imm,
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rcl_scale_src,
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rcl_scale_dst,
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rcl_scale_imm,
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rcr,
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rcr_mem_imm,
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rcr_scale_src,
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rcr_scale_dst,
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rcr_scale_imm,
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shl,
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shl_mem_imm,
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shl_scale_src,
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shl_scale_dst,
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shl_scale_imm,
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sal,
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sal_mem_imm,
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sal_scale_src,
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sal_scale_dst,
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sal_scale_imm,
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shr,
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shr_mem_imm,
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shr_scale_src,
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shr_scale_dst,
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shr_scale_imm,
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sar,
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sar_mem_imm,
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sar_scale_src,
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sar_scale_dst,
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sar_scale_imm,
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sbb,
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sbb_mem_imm,
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sbb_scale_src,
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sbb_scale_dst,
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sbb_scale_imm,
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cmp,
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cmp_mem_imm,
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cmp_scale_src,
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cmp_scale_dst,
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cmp_scale_imm,
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mov,
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mov_mem_imm,
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mov_scale_src,
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mov_scale_dst,
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mov_scale_imm,
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/// ops flags: form:
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/// 0b00 reg1, [reg2 + imm32]
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/// 0b00 reg1, [ds:imm32]
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/// 0b01 reg1, [rip + imm32]
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/// 0b10 reg1, [rip + reloc]
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/// Notes:
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/// * if flags are 0b10, `Data` contains `got_entry` for the linker to generate
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/// a valid relocation for.
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lea,
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lea_scale_src,
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lea_scale_dst,
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lea_scale_imm,
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/// ops flags: form:
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/// 0bX0 reg1
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@ -160,15 +186,6 @@ pub const Inst = struct {
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/// 0b11 reg1, [reg2 + imm32], imm32
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imul_complex,
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/// ops flags: form:
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/// 0bX0 reg1, [rip + imm32]
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/// 0bX1 reg1, [rip + reloc]
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/// Notes:
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/// * if flags are 0bX1, `Data` contains `got_entry` for linker to generate
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/// valid relocation for.
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/// TODO handle more cases
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lea_rip,
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/// ops flags: form:
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/// 0bX0 reg1, imm64
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/// 0bX1 rax, moffs64
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@ -233,16 +250,8 @@ pub const Inst = struct {
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syscall,
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/// ops flags: form:
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/// 0b00 reg1, reg2
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/// 0b00 reg1, imm32
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/// 0b01 reg1, [reg2 + imm32]
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/// 0b01 reg1, [ds:imm32]
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/// 0b10 [reg1 + imm32], reg2
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/// 0b10 [reg1 + 0], imm32
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/// 0b11 [reg1 + imm32], imm32
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/// Notes:
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/// * If reg2 is `none` then it means Data field `imm` is used as the immediate.
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/// * When two imm32 values are required, Data field `payload` points at `ImmPair`.
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/// TODO handle more cases
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@"test",
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/// Breakpoint
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@ -25,6 +25,7 @@ const Type = @import("../../type.zig").Type;
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const fmtIntSizeBin = std.fmt.fmtIntSizeBin;
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mir: Mir,
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bin_file: *link.File,
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pub fn printMir(print: *const Print, w: anytype, mir_to_air_map: std.AutoHashMap(Mir.Inst.Index, Air.Inst.Index), air: Air) !void {
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const instruction_bytes = print.mir.instructions.len *
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@ -64,6 +65,15 @@ pub fn printMir(print: *const Print, w: anytype, mir_to_air_map: std.AutoHashMap
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.sbb => try print.mirArith(.sbb, inst, w),
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.cmp => try print.mirArith(.cmp, inst, w),
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.adc_mem_imm => try print.mirArithMemImm(.adc, inst, w),
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.add_mem_imm => try print.mirArithMemImm(.add, inst, w),
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.sub_mem_imm => try print.mirArithMemImm(.sub, inst, w),
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.xor_mem_imm => try print.mirArithMemImm(.xor, inst, w),
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.and_mem_imm => try print.mirArithMemImm(.@"and", inst, w),
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.or_mem_imm => try print.mirArithMemImm(.@"or", inst, w),
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.sbb_mem_imm => try print.mirArithMemImm(.sbb, inst, w),
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.cmp_mem_imm => try print.mirArithMemImm(.cmp, inst, w),
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.adc_scale_src => try print.mirArithScaleSrc(.adc, inst, w),
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.add_scale_src => try print.mirArithScaleSrc(.add, inst, w),
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.sub_scale_src => try print.mirArithScaleSrc(.sub, inst, w),
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@ -98,7 +108,6 @@ pub fn printMir(print: *const Print, w: anytype, mir_to_air_map: std.AutoHashMap
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.movabs => try print.mirMovabs(inst, w),
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.lea => try print.mirLea(inst, w),
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.lea_rip => try print.mirLeaRip(inst, w),
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.imul_complex => try print.mirIMulComplex(inst, w),
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@ -108,15 +117,15 @@ pub fn printMir(print: *const Print, w: anytype, mir_to_air_map: std.AutoHashMap
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.jmp => try print.mirJmpCall(.jmp, inst, w),
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.call => try print.mirJmpCall(.call, inst, w),
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// .cond_jmp_greater_less => try print.mirCondJmp(.cond_jmp_greater_less, inst, w),
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// .cond_jmp_above_below => try print.mirCondJmp(.cond_jmp_above_below, inst, w),
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// .cond_jmp_eq_ne => try print.mirCondJmp(.cond_jmp_eq_ne, inst, w),
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.cond_jmp_greater_less => try print.mirCondJmp(.cond_jmp_greater_less, inst, w),
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.cond_jmp_above_below => try print.mirCondJmp(.cond_jmp_above_below, inst, w),
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.cond_jmp_eq_ne => try print.mirCondJmp(.cond_jmp_eq_ne, inst, w),
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// .cond_set_byte_greater_less => try print.mirCondSetByte(.cond_set_byte_greater_less, inst, w),
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// .cond_set_byte_above_below => try print.mirCondSetByte(.cond_set_byte_above_below, inst, w),
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// .cond_set_byte_eq_ne => try print.mirCondSetByte(.cond_set_byte_eq_ne, inst, w),
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.cond_set_byte_greater_less => try print.mirCondSetByte(.cond_set_byte_greater_less, inst, w),
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.cond_set_byte_above_below => try print.mirCondSetByte(.cond_set_byte_above_below, inst, w),
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.cond_set_byte_eq_ne => try print.mirCondSetByte(.cond_set_byte_eq_ne, inst, w),
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// .@"test" => try print.mirTest(inst, w),
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.@"test" => try print.mirTest(inst, w),
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.brk => try w.writeAll("brk\n"),
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.ret => try w.writeAll("ret\n"),
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@ -201,254 +210,24 @@ fn mirJmpCall(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: a
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try w.print("{s}\n", .{@tagName(ops.reg1)});
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}
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const CondType = enum {
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/// greater than or equal
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gte,
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/// greater than
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gt,
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/// less than
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lt,
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/// less than or equal
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lte,
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/// above or equal
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ae,
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/// above
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a,
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/// below
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b,
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/// below or equal
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be,
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/// not equal
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ne,
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/// equal
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eq,
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fn fromTagAndFlags(tag: Mir.Inst.Tag, flags: u2) CondType {
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return switch (tag) {
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.cond_jmp_greater_less,
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.cond_set_byte_greater_less,
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=> switch (flags) {
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0b00 => CondType.gte,
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0b01 => CondType.gt,
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0b10 => CondType.lt,
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0b11 => CondType.lte,
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},
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.cond_jmp_above_below,
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.cond_set_byte_above_below,
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=> switch (flags) {
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0b00 => CondType.ae,
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0b01 => CondType.a,
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0b10 => CondType.b,
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0b11 => CondType.be,
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},
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.cond_jmp_eq_ne,
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.cond_set_byte_eq_ne,
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=> switch (@truncate(u1, flags)) {
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0b0 => CondType.ne,
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0b1 => CondType.eq,
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},
|
||||
else => unreachable,
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
inline fn getCondOpCode(tag: Mir.Inst.Tag, cond: CondType) u8 {
|
||||
switch (cond) {
|
||||
.gte => return switch (tag) {
|
||||
.cond_jmp_greater_less => 0x8d,
|
||||
.cond_set_byte_greater_less => 0x9d,
|
||||
else => unreachable,
|
||||
},
|
||||
.gt => return switch (tag) {
|
||||
.cond_jmp_greater_less => 0x8f,
|
||||
.cond_set_byte_greater_less => 0x9f,
|
||||
else => unreachable,
|
||||
},
|
||||
.lt => return switch (tag) {
|
||||
.cond_jmp_greater_less => 0x8c,
|
||||
.cond_set_byte_greater_less => 0x9c,
|
||||
else => unreachable,
|
||||
},
|
||||
.lte => return switch (tag) {
|
||||
.cond_jmp_greater_less => 0x8e,
|
||||
.cond_set_byte_greater_less => 0x9e,
|
||||
else => unreachable,
|
||||
},
|
||||
.ae => return switch (tag) {
|
||||
.cond_jmp_above_below => 0x83,
|
||||
.cond_set_byte_above_below => 0x93,
|
||||
else => unreachable,
|
||||
},
|
||||
.a => return switch (tag) {
|
||||
.cond_jmp_above_below => 0x87,
|
||||
.cond_set_byte_greater_less => 0x97,
|
||||
else => unreachable,
|
||||
},
|
||||
.b => return switch (tag) {
|
||||
.cond_jmp_above_below => 0x82,
|
||||
.cond_set_byte_greater_less => 0x92,
|
||||
else => unreachable,
|
||||
},
|
||||
.be => return switch (tag) {
|
||||
.cond_jmp_above_below => 0x86,
|
||||
.cond_set_byte_greater_less => 0x96,
|
||||
else => unreachable,
|
||||
},
|
||||
.eq => return switch (tag) {
|
||||
.cond_jmp_eq_ne => 0x84,
|
||||
.cond_set_byte_eq_ne => 0x94,
|
||||
else => unreachable,
|
||||
},
|
||||
.ne => return switch (tag) {
|
||||
.cond_jmp_eq_ne => 0x85,
|
||||
.cond_set_byte_eq_ne => 0x95,
|
||||
else => unreachable,
|
||||
},
|
||||
}
|
||||
}
|
||||
|
||||
fn mirCondJmp(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
_ = w; // TODO
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
const target = print.mir.instructions.items(.data)[inst].inst;
|
||||
const cond = CondType.fromTagAndFlags(tag, ops.flags);
|
||||
const opc = getCondOpCode(tag, cond);
|
||||
const source = print.code.items.len;
|
||||
const encoder = try Encoder.init(print.code, 6);
|
||||
encoder.opcode_2byte(0x0f, opc);
|
||||
try print.relocs.append(print.bin_file.allocator, .{
|
||||
.source = source,
|
||||
.target = target,
|
||||
.offset = print.code.items.len,
|
||||
.length = 6,
|
||||
});
|
||||
encoder.imm32(0);
|
||||
_ = print;
|
||||
_ = tag;
|
||||
_ = inst;
|
||||
try w.writeAll("TODO print mirCondJmp\n");
|
||||
}
|
||||
|
||||
fn mirCondSetByte(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
_ = w; // TODO
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
const cond = CondType.fromTagAndFlags(tag, ops.flags);
|
||||
const opc = getCondOpCode(tag, cond);
|
||||
const encoder = try Encoder.init(print.code, 4);
|
||||
encoder.rex(.{
|
||||
.w = true,
|
||||
.b = ops.reg1.isExtended(),
|
||||
});
|
||||
encoder.opcode_2byte(0x0f, opc);
|
||||
encoder.modRm_direct(0x0, ops.reg1.lowId());
|
||||
_ = tag;
|
||||
_ = inst;
|
||||
_ = print;
|
||||
try w.writeAll("TODO print mirCondSetByte\n");
|
||||
}
|
||||
|
||||
fn mirTest(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
_ = w; // TODO
|
||||
const tag = print.mir.instructions.items(.tag)[inst];
|
||||
assert(tag == .@"test");
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
switch (ops.flags) {
|
||||
0b00 => blk: {
|
||||
if (ops.reg2 == .none) {
|
||||
// TEST r/m64, imm32
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
if (ops.reg1.to64() == .rax) {
|
||||
// TODO reduce the size of the instruction if the immediate
|
||||
// is smaller than 32 bits
|
||||
const encoder = try Encoder.init(print.code, 6);
|
||||
encoder.rex(.{
|
||||
.w = true,
|
||||
});
|
||||
encoder.opcode_1byte(0xa9);
|
||||
encoder.imm32(imm);
|
||||
break :blk;
|
||||
}
|
||||
const opc: u8 = if (ops.reg1.size() == 8) 0xf6 else 0xf7;
|
||||
const encoder = try Encoder.init(print.code, 7);
|
||||
encoder.rex(.{
|
||||
.w = true,
|
||||
.b = ops.reg1.isExtended(),
|
||||
});
|
||||
encoder.opcode_1byte(opc);
|
||||
encoder.modRm_direct(0, ops.reg1.lowId());
|
||||
encoder.imm8(@intCast(i8, imm));
|
||||
break :blk;
|
||||
}
|
||||
// TEST r/m64, r64
|
||||
return print.fail("TODO TEST r/m64, r64", .{});
|
||||
},
|
||||
else => return print.fail("TODO more TEST alternatives", .{}),
|
||||
}
|
||||
}
|
||||
|
||||
const EncType = enum {
|
||||
/// OP r/m64, imm32
|
||||
mi,
|
||||
|
||||
/// OP r/m64, r64
|
||||
mr,
|
||||
|
||||
/// OP r64, r/m64
|
||||
rm,
|
||||
};
|
||||
|
||||
const OpCode = struct {
|
||||
opc: u8,
|
||||
/// Only used if `EncType == .mi`.
|
||||
modrm_ext: u3,
|
||||
};
|
||||
|
||||
inline fn getArithOpCode(tag: Mir.Inst.Tag, enc: EncType) OpCode {
|
||||
switch (enc) {
|
||||
.mi => return switch (tag) {
|
||||
.adc => .{ .opc = 0x81, .modrm_ext = 0x2 },
|
||||
.add => .{ .opc = 0x81, .modrm_ext = 0x0 },
|
||||
.sub => .{ .opc = 0x81, .modrm_ext = 0x5 },
|
||||
.xor => .{ .opc = 0x81, .modrm_ext = 0x6 },
|
||||
.@"and" => .{ .opc = 0x81, .modrm_ext = 0x4 },
|
||||
.@"or" => .{ .opc = 0x81, .modrm_ext = 0x1 },
|
||||
.sbb => .{ .opc = 0x81, .modrm_ext = 0x3 },
|
||||
.cmp => .{ .opc = 0x81, .modrm_ext = 0x7 },
|
||||
.mov => .{ .opc = 0xc7, .modrm_ext = 0x0 },
|
||||
else => unreachable,
|
||||
},
|
||||
.mr => {
|
||||
const opc: u8 = switch (tag) {
|
||||
.adc => 0x11,
|
||||
.add => 0x01,
|
||||
.sub => 0x29,
|
||||
.xor => 0x31,
|
||||
.@"and" => 0x21,
|
||||
.@"or" => 0x09,
|
||||
.sbb => 0x19,
|
||||
.cmp => 0x39,
|
||||
.mov => 0x89,
|
||||
else => unreachable,
|
||||
};
|
||||
return .{ .opc = opc, .modrm_ext = undefined };
|
||||
},
|
||||
.rm => {
|
||||
const opc: u8 = switch (tag) {
|
||||
.adc => 0x13,
|
||||
.add => 0x03,
|
||||
.sub => 0x2b,
|
||||
.xor => 0x33,
|
||||
.@"and" => 0x23,
|
||||
.@"or" => 0x0b,
|
||||
.sbb => 0x1b,
|
||||
.cmp => 0x3b,
|
||||
.mov => 0x8b,
|
||||
else => unreachable,
|
||||
};
|
||||
return .{ .opc = opc, .modrm_ext = undefined };
|
||||
},
|
||||
}
|
||||
_ = print;
|
||||
_ = inst;
|
||||
try w.writeAll("TODO print mirTest\n");
|
||||
}
|
||||
|
||||
fn mirArith(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
@ -465,31 +244,63 @@ fn mirArith(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: any
|
||||
0b01 => {
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
if (ops.reg2 == .none) {
|
||||
try w.print("{s}, [ds:{d}]", .{ @tagName(ops.reg1), imm });
|
||||
try w.print("{s}, ", .{@tagName(ops.reg1)});
|
||||
switch (ops.reg1.size()) {
|
||||
8 => try w.print("byte ptr ", .{}),
|
||||
16 => try w.print("word ptr ", .{}),
|
||||
32 => try w.print("dword ptr ", .{}),
|
||||
64 => try w.print("qword ptr ", .{}),
|
||||
else => unreachable,
|
||||
}
|
||||
try w.print("[ds:{d}]", .{imm});
|
||||
} else {
|
||||
try w.print("{s}, [{s} + {d}]", .{ @tagName(ops.reg1), @tagName(ops.reg2), imm });
|
||||
try w.print("{s}, ", .{@tagName(ops.reg1)});
|
||||
switch (ops.reg1.size()) {
|
||||
8 => try w.print("byte ptr ", .{}),
|
||||
16 => try w.print("word ptr ", .{}),
|
||||
32 => try w.print("dword ptr ", .{}),
|
||||
64 => try w.print("qword ptr ", .{}),
|
||||
else => unreachable,
|
||||
}
|
||||
try w.print("[{s} + {d}]", .{ @tagName(ops.reg2), imm });
|
||||
}
|
||||
},
|
||||
0b10 => {
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
if (ops.reg2 == .none) {
|
||||
try w.print("[{s} + 0], {d}", .{ @tagName(ops.reg1), imm });
|
||||
try w.writeAll("unused variant");
|
||||
} else {
|
||||
switch (ops.reg2.size()) {
|
||||
8 => try w.print("byte ptr ", .{}),
|
||||
16 => try w.print("word ptr ", .{}),
|
||||
32 => try w.print("dword ptr ", .{}),
|
||||
64 => try w.print("qword ptr ", .{}),
|
||||
else => unreachable,
|
||||
}
|
||||
try w.print("[{s} + {d}], {s}", .{ @tagName(ops.reg1), imm, @tagName(ops.reg2) });
|
||||
}
|
||||
},
|
||||
0b11 => {
|
||||
if (ops.reg2 == .none) {
|
||||
const payload = print.mir.instructions.items(.data)[inst].payload;
|
||||
const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data;
|
||||
try w.print("[{s} + {d}], {d}", .{ @tagName(ops.reg1), imm_pair.dest_off, imm_pair.operand });
|
||||
}
|
||||
try w.writeAll("TODO");
|
||||
try w.writeAll("unused variant");
|
||||
},
|
||||
}
|
||||
try w.writeByte('\n');
|
||||
}
|
||||
|
||||
fn mirArithMemImm(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
const payload = print.mir.instructions.items(.data)[inst].payload;
|
||||
const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data;
|
||||
try w.print("{s} ", .{@tagName(tag)});
|
||||
switch (ops.flags) {
|
||||
0b00 => try w.print("byte ptr ", .{}),
|
||||
0b01 => try w.print("word ptr ", .{}),
|
||||
0b10 => try w.print("dword ptr ", .{}),
|
||||
0b11 => try w.print("qword ptr ", .{}),
|
||||
}
|
||||
try w.print("[{s} + {d}], {d}\n", .{ @tagName(ops.reg1), imm_pair.dest_off, imm_pair.operand });
|
||||
}
|
||||
|
||||
fn mirArithScaleSrc(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
const scale = ops.flags;
|
||||
@ -560,19 +371,57 @@ fn mirIMulComplex(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
}
|
||||
|
||||
fn mirLea(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
const tag = print.mir.instructions.items(.tag)[inst];
|
||||
assert(tag == .lea);
|
||||
const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]);
|
||||
assert(ops.flags == 0b01);
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
|
||||
try w.print("lea {s} [{s} + {d}]\n", .{ @tagName(ops.reg1), @tagName(ops.reg2), imm });
|
||||
}
|
||||
|
||||
fn mirLeaRip(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
_ = print;
|
||||
_ = inst;
|
||||
return w.writeAll("TODO lea_rip\n");
|
||||
try w.writeAll("lea ");
|
||||
switch (ops.flags) {
|
||||
0b00 => {
|
||||
const imm = print.mir.instructions.items(.data)[inst].imm;
|
||||
try w.print("{s} [", .{@tagName(ops.reg1)});
|
||||
if (ops.reg2 != .none) {
|
||||
try w.print("{s} + ", .{@tagName(ops.reg2)});
|
||||
} else {
|
||||
try w.print("ds:", .{});
|
||||
}
|
||||
try w.print("{d}]\n", .{imm});
|
||||
},
|
||||
0b01 => {
|
||||
try w.print("{s}, ", .{@tagName(ops.reg1)});
|
||||
switch (ops.reg1.size()) {
|
||||
8 => try w.print("byte ptr ", .{}),
|
||||
16 => try w.print("word ptr ", .{}),
|
||||
32 => try w.print("dword ptr ", .{}),
|
||||
64 => try w.print("qword ptr ", .{}),
|
||||
else => unreachable,
|
||||
}
|
||||
try w.print("[rip + 0x0] ", .{});
|
||||
const payload = print.mir.instructions.items(.data)[inst].payload;
|
||||
const imm = print.mir.extraData(Mir.Imm64, payload).data.decode();
|
||||
try w.print("target@{x}", .{imm});
|
||||
},
|
||||
0b10 => {
|
||||
try w.print("{s}, ", .{@tagName(ops.reg1)});
|
||||
switch (ops.reg1.size()) {
|
||||
8 => try w.print("byte ptr ", .{}),
|
||||
16 => try w.print("word ptr ", .{}),
|
||||
32 => try w.print("dword ptr ", .{}),
|
||||
64 => try w.print("qword ptr ", .{}),
|
||||
else => unreachable,
|
||||
}
|
||||
try w.print("[rip + 0x0] ", .{});
|
||||
const got_entry = print.mir.instructions.items(.data)[inst].got_entry;
|
||||
if (print.bin_file.cast(link.File.MachO)) |macho_file| {
|
||||
const target = macho_file.locals.items[got_entry];
|
||||
const target_name = macho_file.getString(target.n_strx);
|
||||
try w.print("target@{s}", .{target_name});
|
||||
} else {
|
||||
try w.writeAll("TODO lea reg, [rip + reloc] for linking backends different than MachO");
|
||||
}
|
||||
},
|
||||
0b11 => {
|
||||
try w.writeAll("unused variant\n");
|
||||
},
|
||||
}
|
||||
try w.writeAll("\n");
|
||||
}
|
||||
|
||||
fn mirCallExtern(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void {
|
||||
|
||||
@ -1604,6 +1604,64 @@ pub fn addCases(ctx: *TestContext) !void {
|
||||
":2:28: error: cannot set address space of local variable 'foo'",
|
||||
});
|
||||
}
|
||||
|
||||
{
|
||||
var case = ctx.exe("saving vars of different ABI size to stack", target);
|
||||
|
||||
case.addCompareOutput(
|
||||
\\pub fn main() void {
|
||||
\\ assert(callMe(2) == 24);
|
||||
\\}
|
||||
\\
|
||||
\\fn callMe(a: u8) u8 {
|
||||
\\ var b: u8 = a + 10;
|
||||
\\ const c = 2 * b;
|
||||
\\ return c;
|
||||
\\}
|
||||
\\
|
||||
\\pub fn assert(ok: bool) void {
|
||||
\\ if (!ok) unreachable; // assertion failure
|
||||
\\}
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
case.addCompareOutput(
|
||||
\\pub fn main() void {
|
||||
\\ assert(callMe(2) == 24);
|
||||
\\}
|
||||
\\
|
||||
\\fn callMe(a: u16) u16 {
|
||||
\\ var b: u16 = a + 10;
|
||||
\\ const c = 2 * b;
|
||||
\\ return c;
|
||||
\\}
|
||||
\\
|
||||
\\pub fn assert(ok: bool) void {
|
||||
\\ if (!ok) unreachable; // assertion failure
|
||||
\\}
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
case.addCompareOutput(
|
||||
\\pub fn main() void {
|
||||
\\ assert(callMe(2) == 24);
|
||||
\\}
|
||||
\\
|
||||
\\fn callMe(a: u32) u32 {
|
||||
\\ var b: u32 = a + 10;
|
||||
\\ const c = 2 * b;
|
||||
\\ return c;
|
||||
\\}
|
||||
\\
|
||||
\\pub fn assert(ok: bool) void {
|
||||
\\ if (!ok) unreachable; // assertion failure
|
||||
\\}
|
||||
,
|
||||
"",
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user