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stage2: lower 1-byte and 2-byte values saved to stack
* fix handling of `ah`, `bh`, `ch`, and `dh` registers (which are actually used as aliases to `dil`, etc. registers). Currenly, we treat them as aliases only meaning when we encounter `ah` we make sure to set the REX.W to promote the instruction to 64bits and use `dil` register instead - otherwise we might have mismatch between registers used in different parts of the codegen. In the future, we can and should use `ah`, etc. as upper 8bit halves of 16bit registers `ax`, etc. * fix bug in `airCmp` where `.cmp` MIR instruction shouldn't force type `Bool` but let the type of the original type propagate downwards - we need this to make an informed choice of the target register size and hence choose the right encoding down the line. * implement lowering of 1-byte and 2-byte values to stack and add matching stage2 tests for x86_64 codegen
This commit is contained in:
Jakub Konka
parent
08ea1a2eab
commit
b7e2235973
@ -1642,11 +1642,11 @@ fn genBinMathOpMir(
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});
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},
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.immediate => |imm| {
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// TODO I am not quite sure why we need to set the size of the register here...
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const abi_size = dst_ty.abiSize(self.target.*);
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_ = try self.addInst(.{
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.tag = mir_tag,
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.ops = (Mir.Ops{
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.reg1 = dst_reg.to32(),
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.reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),
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}).encode(),
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.data = .{ .imm = @intCast(i32, imm) },
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});
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@ -1751,13 +1751,14 @@ fn genIMulOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !
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});
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},
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.immediate => |imm| {
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// TODO take into account the type's ABI size when selecting the register alias
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// register, immediate
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if (imm <= math.maxInt(i32)) {
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_ = try self.addInst(.{
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.tag = .imul_complex,
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.ops = (Mir.Ops{
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.reg1 = dst_reg,
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.reg2 = dst_reg,
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.reg1 = dst_reg.to32(),
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.reg2 = dst_reg.to32(),
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = @intCast(i32, imm) },
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@ -2147,7 +2148,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
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// This instruction supports only signed 32-bit immediates at most.
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const src_mcv = try self.limitImmediateType(bin_op.rhs, i32);
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try self.genBinMathOpMir(.cmp, Type.initTag(.bool), dst_mcv, src_mcv);
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try self.genBinMathOpMir(.cmp, ty, dst_mcv, src_mcv);
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break :result switch (ty.isSignedInt()) {
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true => MCValue{ .compare_flags_signed = op },
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false => MCValue{ .compare_flags_unsigned = op },
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@ -2792,16 +2793,10 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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return self.fail("TODO implement set stack variable with large stack offset", .{});
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}
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switch (abi_size) {
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1 => {
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return self.fail("TODO implement set abi_size=1 stack variable with immediate", .{});
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},
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2 => {
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return self.fail("TODO implement set abi_size=2 stack variable with immediate", .{});
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},
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4 => {
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1, 2, 4 => {
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// We have a positive stack offset value but we want a twos complement negative
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// offset from rbp, which is at the top of the stack frame.
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// mov DWORD PTR [rbp+offset], immediate
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// mov [rbp+offset], immediate
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const payload = try self.addExtra(Mir.ImmPair{
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.dest_off = -@intCast(i32, adj_off),
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.operand = @bitCast(i32, @intCast(u32, x_big)),
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@ -2810,7 +2805,12 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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.tag = .mov_mem_imm,
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.ops = (Mir.Ops{
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.reg1 = .rbp,
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.flags = 0b10,
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.flags = switch (abi_size) {
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1 => 0b00,
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2 => 0b01,
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4 => 0b10,
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else => unreachable,
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},
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}).encode(),
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.data = .{ .payload = payload },
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});
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@ -2954,11 +2954,12 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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return;
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}
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if (x <= math.maxInt(i32)) {
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const abi_size = ty.abiSize(self.target.*);
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// Next best case: if we set the lower four bytes, the upper four will be zeroed.
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = reg.to32(),
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.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
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}).encode(),
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.data = .{ .imm = @intCast(i32, x) },
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});
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@ -468,7 +468,15 @@ fn mirArithMemImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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) catch |err| emit.failWithLoweringError(err);
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}
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fn immOpSize(imm: i64) u8 {
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inline fn setRexWRegister(reg: Register) bool {
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if (reg.size() == 64) return true;
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return switch (reg) {
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.ah, .bh, .ch, .dh => true,
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else => false,
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};
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}
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inline fn immOpSize(imm: i64) u8 {
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blk: {
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_ = math.cast(i8, imm) catch break :blk;
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return 8;
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@ -1370,7 +1378,10 @@ fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8))
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encoder.opcode_1byte(0x66);
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}
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encoder.rex(.{
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.w = tag.isSetCC(),
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.w = switch (reg) {
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.ah, .bh, .ch, .dh => true,
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else => false,
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},
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.b = reg.isExtended(),
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});
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opc.encode(encoder);
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@ -1389,7 +1400,7 @@ fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8))
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return error.OperandSizeMismatch;
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}
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encoder.rex(.{
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.w = tag.isSetCC(),
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.w = false,
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.b = reg.isExtended(),
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});
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opc.encode(encoder);
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@ -1455,7 +1466,7 @@ fn lowerToTdFdEnc(tag: Tag, reg: Register, moffs: i64, code: *std.ArrayList(u8),
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encoder.opcode_1byte(0x66);
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}
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encoder.rex(.{
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.w = reg.size() == 64,
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.w = setRexWRegister(reg),
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});
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opc.encode(encoder);
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switch (reg.size()) {
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@ -1488,7 +1499,7 @@ fn lowerToOiEnc(tag: Tag, reg: Register, imm: i64, code: *std.ArrayList(u8)) Low
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encoder.opcode_1byte(0x66);
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}
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encoder.rex(.{
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.w = reg.size() == 64,
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.w = setRexWRegister(reg),
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.b = reg.isExtended(),
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});
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opc.encodeWithReg(encoder, reg);
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@ -1525,7 +1536,7 @@ fn lowerToMiEnc(tag: Tag, reg_or_mem: RegisterOrMemory, imm: i32, code: *std.Arr
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encoder.opcode_1byte(0x66);
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}
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encoder.rex(.{
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.w = dst_reg.size() == 64,
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.w = setRexWRegister(dst_reg),
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.b = dst_reg.isExtended(),
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});
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opc.encode(encoder);
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@ -1623,7 +1634,7 @@ fn lowerToRmEnc(
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}
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const encoder = try Encoder.init(code, 3);
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encoder.rex(.{
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.w = reg.size() == 64,
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.w = setRexWRegister(reg) or setRexWRegister(src_reg),
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.r = reg.isExtended(),
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.b = src_reg.isExtended(),
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});
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@ -1645,7 +1656,7 @@ fn lowerToRmEnc(
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return error.OperandSizeMismatch;
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}
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encoder.rex(.{
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.w = reg.size() == 64,
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.w = setRexWRegister(reg),
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.r = reg.isExtended(),
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.b = src_reg.isExtended(),
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});
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@ -1676,7 +1687,7 @@ fn lowerToRmEnc(
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}
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} else {
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encoder.rex(.{
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.w = reg.size() == 64,
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.w = setRexWRegister(reg),
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.r = reg.isExtended(),
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});
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opc.encode(encoder);
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@ -1706,7 +1717,7 @@ fn lowerToMrEnc(
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}
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const encoder = try Encoder.init(code, 3);
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encoder.rex(.{
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.w = dst_reg.size() == 64,
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.w = setRexWRegister(dst_reg) or setRexWRegister(reg),
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.r = reg.isExtended(),
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.b = dst_reg.isExtended(),
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});
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@ -1726,7 +1737,7 @@ fn lowerToMrEnc(
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return error.OperandSizeMismatch;
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}
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encoder.rex(.{
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.w = dst_mem.ptr_size == .qword_ptr,
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.w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
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.r = reg.isExtended(),
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.b = dst_reg.isExtended(),
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});
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@ -1757,7 +1768,7 @@ fn lowerToMrEnc(
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}
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} else {
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encoder.rex(.{
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.w = dst_mem.ptr_size == .qword_ptr,
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.w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
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.r = reg.isExtended(),
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});
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opc.encode(encoder);
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@ -1794,7 +1805,7 @@ fn lowerToRmiEnc(
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return error.OperandSizeMismatch;
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}
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encoder.rex(.{
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.w = reg.size() == 64,
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.w = setRexWRegister(reg) or setRexWRegister(src_reg),
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.r = reg.isExtended(),
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.b = src_reg.isExtended(),
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});
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@ -1812,7 +1823,7 @@ fn lowerToRmiEnc(
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return error.OperandSizeMismatch;
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}
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encoder.rex(.{
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.w = reg.size() == 64,
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.w = setRexWRegister(reg),
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.r = reg.isExtended(),
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.b = src_reg.isExtended(),
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});
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@ -1843,7 +1854,7 @@ fn lowerToRmiEnc(
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}
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} else {
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encoder.rex(.{
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.w = reg.size() == 64,
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.w = setRexWRegister(reg),
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.r = reg.isExtended(),
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});
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opc.encode(encoder);
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@ -2089,7 +2100,7 @@ test "lower M encoding" {
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try lowerToMEnc(.jmp_near, RegisterOrMemory.mem(null, 0x10, .qword_ptr), code.buffer());
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try expectEqualHexStrings("\xFF\x24\x25\x10\x00\x00\x00", code.emitted(), "jmp qword ptr [ds:0x10]");
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try lowerToMEnc(.seta, RegisterOrMemory.reg(.r11b), code.buffer());
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try expectEqualHexStrings("\x49\x0F\x97\xC3", code.emitted(), "seta r11b");
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try expectEqualHexStrings("\x41\x0F\x97\xC3", code.emitted(), "seta r11b");
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}
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test "lower O encoding" {
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@ -2111,9 +2122,9 @@ test "lower RMI encoding" {
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"imul rax, qword ptr [rbp - 8], 0x10",
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);
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try lowerToRmiEnc(.imul, .eax, RegisterOrMemory.mem(.rbp, -4, .dword_ptr), 0x10, code.buffer());
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try expectEqualHexStrings("\x69\x45\xFC\x10\x00\x00\x00", code.emitted(), "imul ax, [rbp - 2], 0x10");
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try expectEqualHexStrings("\x69\x45\xFC\x10\x00\x00\x00", code.emitted(), "imul eax, dword ptr [rbp - 4], 0x10");
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try lowerToRmiEnc(.imul, .ax, RegisterOrMemory.mem(.rbp, -2, .word_ptr), 0x10, code.buffer());
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try expectEqualHexStrings("\x66\x69\x45\xFE\x10\x00", code.emitted(), "imul eax, [rbp - 4], 0x10");
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try expectEqualHexStrings("\x66\x69\x45\xFE\x10\x00", code.emitted(), "imul ax, word ptr [rbp - 2], 0x10");
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try lowerToRmiEnc(.imul, .r12, RegisterOrMemory.reg(.r12), 0x10, code.buffer());
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try expectEqualHexStrings("\x4D\x69\xE4\x10\x00\x00\x00", code.emitted(), "imul r12, r12, 0x10");
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try lowerToRmiEnc(.imul, .r12w, RegisterOrMemory.reg(.r12w), 0x10, code.buffer());
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@ -1604,6 +1604,64 @@ pub fn addCases(ctx: *TestContext) !void {
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":2:28: error: cannot set address space of local variable 'foo'",
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});
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}
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{
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var case = ctx.exe("saving vars of different ABI size to stack", target);
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case.addCompareOutput(
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\\pub fn main() void {
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\\ assert(callMe(2) == 24);
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\\}
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\\
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\\fn callMe(a: u8) u8 {
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\\ var b: u8 = a + 10;
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\\ const c = 2 * b;
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\\ return c;
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\\}
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\\
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\\pub fn assert(ok: bool) void {
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\\ if (!ok) unreachable; // assertion failure
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\\}
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,
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"",
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);
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case.addCompareOutput(
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\\pub fn main() void {
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\\ assert(callMe(2) == 24);
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\\}
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\\
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\\fn callMe(a: u16) u16 {
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\\ var b: u16 = a + 10;
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\\ const c = 2 * b;
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\\ return c;
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\\}
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\\
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\\pub fn assert(ok: bool) void {
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\\ if (!ok) unreachable; // assertion failure
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\\}
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,
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"",
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);
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case.addCompareOutput(
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\\pub fn main() void {
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\\ assert(callMe(2) == 24);
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\\}
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\\
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\\fn callMe(a: u32) u32 {
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\\ var b: u32 = a + 10;
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\\ const c = 2 * b;
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\\ return c;
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\\}
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\\
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\\pub fn assert(ok: bool) void {
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\\ if (!ok) unreachable; // assertion failure
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\\}
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,
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"",
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);
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}
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}
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}
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