14742 Commits

Author SHA1 Message Date
Jakub Konka
d31eb744ce link/macho: fix 32bit build 2024-05-23 12:04:17 +02:00
Jakub Konka
f3a503eca2 link/macho: ensure we set alignment of literals to max alignment 2024-05-23 12:04:17 +02:00
Jakub Konka
71bbc5efc9 link/macho: print error message when hitting unexpected remainder error 2024-05-23 12:04:17 +02:00
Jakub Konka
8fc0c7dce1 link/macho: apply fixes to deduping logic
* test non-ObjC literal deduping logic
2024-05-23 12:04:17 +02:00
Jakub Konka
434e69482e link/macho: dedup literals in objects and internal object file 2024-05-23 12:04:17 +02:00
Andrew Kelley
9be8a9000f Revert "implement @expect builtin (#19658)"
This reverts commit a7de02e05216db9a04e438703ddf1b6b12f3fbef.

This did not implement the accepted proposal, and I did not sign off
on the changes. I would like a chance to review this, please.
2024-05-22 09:57:43 -07:00
David Rubin
a7de02e052
implement @expect builtin (#19658)
* implement `@expect`

* add docs

* add a second arg for expected bool

* fix typo

* move `expect` to use BinOp

* update to newer langref format
2024-05-22 10:51:16 -05:00
Jacob Young
ed75f62568 Compilation: better cleanup of temporary files
The diag file did not get deleted on the success path and the dep file
did not get deleted on the failure path.
2024-05-22 10:42:01 -04:00
Veikka Tuominen
0fb2015fd3 llvm: fix @wasmMemory{Size,Grow} for wasm64
Closes #19942
2024-05-22 09:48:52 -04:00
Veikka Tuominen
5fe9f88b13
Merge pull request #20023 from Vexu/fixes
Minor LLVM backend fixes
2024-05-22 11:54:38 +03:00
Veikka Tuominen
eb0f871cb9
Merge pull request #19961 from wooster0/errorstuff
Sema: improvements to error messages related to the handling of (error) values
2024-05-21 22:37:00 +03:00
wooster0
ac55685a94 Sema: add missing declared here note 2024-05-22 02:16:56 +09:00
Veikka Tuominen
f776e70c39 llvm: fix lowering of packed structs with optional pointers
Closes #20022
2024-05-21 19:52:25 +03:00
Veikka Tuominen
167854c19c llvm: lower ptr to int constants with correct address spaces
Closes #19915
2024-05-21 19:52:00 +03:00
Veikka Tuominen
8aae0d87b5 Target: add OpenHarmonyOS ABI
Closes #20009
2024-05-20 09:25:52 -04:00
Wooster
f14cf13ff8 Sema: suggest using try/catch/if on method call on error union 2024-05-14 01:13:49 +09:00
r00ster91
9ae43567a3 Sema: improve error set/union discard/ignore errors
Previously the error had a note suggesting to use `try`, `catch`, or
`if`, even for error sets where none of those work.
Instead, in case of an error set the way you can handle the error
depends very much on the specific case. For example you might be in a
`catch` where you are discarding or ignoring the error set capture
value, in which case one way to handle the error might be to `return`
the error.
So, in that case, we do not attach that error note.

Additionally, this makes the error tell you what kind of an error it is:
is it an error set or an error union? This distinction is very relevant
in how to handle the error.
2024-05-14 01:13:49 +09:00
r00ster91
8579904ddd Sema: add error note for !?Type types when optional type is expected 2024-05-14 01:13:49 +09:00
r00ster91
31689d0dd9 Sema: remove periods from the few error messages that have them
For consistency.
2024-05-14 01:13:49 +09:00
r00ster91
60830e36e3 Sema error: talk about discarding instead of suppressing
Maybe I'm just being pedantic here (most likely) but I don't like how we're
just telling the user here how to "suppress this error" by "assigning the value to '_'".
I think it's better if we use the word "discard" here which I think is
the official terminology and also tells the user what it actually means
to "assign the value to '_'".

Also, using the value would also be a way to "suppress the error".
It is just one of the two options: discard or use.
2024-05-14 01:13:48 +09:00
Christofer Nolander
8f6b1f2c38
zig fetch: resolve branch/tag names to commit SHA (#19941)
* Revert "Revert "Merge pull request #19349 from nolanderc/save-commit""

This reverts commit 6ca4ed5948d8eaab28fc5e3706aeb1b113a210af.

* update to new URI changes, rework `--save` type

* initialize `latest_commit` to null everywhere
2024-05-11 14:19:35 -07:00
David Rubin
1dfdc21c31 riscv: intcast got_addr
the recent merge strings PR made `got_addr` `i64` and now requires an `@intCast`.
2024-05-11 02:17:24 -07:00
David Rubin
ffb63a05a3 riscv: finally fix bug + airAggregateInit
i just hadn't realized that I placed the `riscv_start` branch in the non-simplified
starts
2024-05-11 02:17:24 -07:00
David Rubin
2fd83d8c0a riscv: by-value structs + @min 2024-05-11 02:17:24 -07:00
David Rubin
a30af172e8 riscv: math progress 2024-05-11 02:17:24 -07:00
David Rubin
a615fbc1f8 riscv: mutable globals 2024-05-11 02:17:24 -07:00
David Rubin
d9e0cafe64 riscv: add stage2_riscv to test matrix and bypass failing tests 2024-05-11 02:17:24 -07:00
David Rubin
e622485df8 riscv: actually working test runner 2024-05-11 02:17:11 -07:00
David Rubin
d19b77d63f riscv: back to hello world panics 2024-05-11 02:17:11 -07:00
David Rubin
cc204e2365 riscv: spill args immediately to prevent clobbers 2024-05-11 02:17:11 -07:00
David Rubin
6740c1f084 riscv: big rewrite to use latest liveness
this one is even harder to document then the last large overhaul.

TLDR;
- split apart Emit.zig into an Emit.zig and a Lower.zig
- created seperate files for the encoding, and now adding a new instruction
is as simple as just adding it to a couple of switch statements and providing the encoding.
- relocs are handled in a more sane maner, and we have a clear defining boundary between
lea_symbol and load_symbol now.
- a lot of different abstractions for things like the stack, memory, registers, and others.
- we're using x86_64's FrameIndex now, which simplifies a lot of the tougher design process.
- a lot more that I don't have the energy to document. at this point, just read the commit itself :p
2024-05-11 02:17:11 -07:00
David Rubin
9d0bb6371d riscv: almost @errorName but not loading correctly 2024-05-11 02:17:11 -07:00
David Rubin
8ac239ebce riscv: add enough components to get a test runner working 2024-05-11 02:17:11 -07:00
David Rubin
c0629c3539 riscv: implement airNot 2024-05-11 02:17:11 -07:00
David Rubin
4ce85f930e riscv: implement structFieldPtr and retLoad 2024-05-11 02:17:11 -07:00
David Rubin
ece70e08a0 riscv: pass optionals by register_pair for resolveCallingConventionValues 2024-05-11 02:17:11 -07:00
David Rubin
26ce82d98e riscv: correctly derefence load_symbol in genSetReg 2024-05-11 02:17:11 -07:00
David Rubin
3bf008a3d0 riscv: implement slices 2024-05-11 02:17:11 -07:00
David Rubin
350ad90cee riscv: totally rewrite how we do loads and stores
this commit is a little too large to document fully, however the main gist of it this

- finish the `genInlineMemcpy` implement
- rename `setValue` to `genCopy` as I agree with jacob that it's a better name
- add in `genVarDbgInfo` for a better gdb experience
- follow the x86_64's method for genCall, as the procedure is very similar for us
- add `airSliceLen` as it's trivial
- change up the `airAddWithOverflow implementation a bit
- make sure to not spill of the elem_ty is 0 size
- correctly follow the RISC-V calling convention and spill the used calle saved registers in the prologue
and restore them in the epilogue
- add `address`, `deref`, and `offset` helper functions for MCValue. I must say I love these,
they make the code very readable and super verbose :)
- fix a `register_manager.zig` issue where when using the last register in the set, the value would overflow at comptime.
was happening because we were adding to `max_id` before subtracting from it.
2024-05-11 02:17:11 -07:00
David Rubin
3c0015c828 riscv: implement a basic @intCast
the truncation panic logic is generated in Sema, so I don't need to roll anything
of my own. I add all of the boilerplate for that detecting the truncation and it works
in basic test cases!
2024-05-11 02:17:11 -07:00
David Rubin
685f828218 riscv: add a custom panic function
this provides a much better indication of when we are having a controlled panic with an error message
or when we are actually segfaulting, as before the `trap` as causing a segfault.
2024-05-11 02:17:11 -07:00
David Rubin
b28c966e33 riscv: fix overflow checks in addition. 2024-05-11 02:17:11 -07:00
David Rubin
e70584e2f8 riscv: change load_symbol psuedo instruction size to 8 2024-05-11 02:17:11 -07:00
David Rubin
06089fc89a riscv: fix how we calculate stack offsets. allows for pass by reference arguments. 2024-05-11 02:17:11 -07:00
David Rubin
c96989aa4b riscv: correctly index struct field access
when the struct is in stack memory, we access it using a byte-offset,
because that's how the stack works. on the other hand when the struct
is in a register, we are working with bits and the field offset should
be a bit offset.
2024-05-11 02:17:11 -07:00
David Rubin
09b7aabe09 riscv: add allocReg helper, and clean up some comparing logic
- Added the basic framework for panicing with an overflow in `airAddWithOverflow`, but there is no check done yet.
- added the `cmp_lt`, `cmp_gte`, and `cmp_imm_eq` MIR instructions, and their respective functionality.
2024-05-11 02:17:11 -07:00
David Rubin
08452b1add riscv: correct the order of the return epilogue 2024-05-11 02:17:11 -07:00
David Rubin
f1fe5c937e riscv: pointer work
lots of thinking later, ive begun to grasp my head around how the pointers should work. this commit allows basic pointer loading and storing to happen.
2024-05-11 02:17:11 -07:00
David Rubin
9229321400 riscv: change up how we do args
- before we were storing each arg in it's own function arg register. with this commit now we store the args in the fa register before calling as per the RISC-V calling convention, however as soon as we enter the callee, aka in airArg, we spill the argument to the stack. this allows us to spend less effort worrying about whether we're going to clobber the function arguments when another function is called inside of the callee.

- we were actually clobbering the fa regs inside of resolveCallingConvetion, because of the null argument to allocReg. now each lock is stored in an array which is then iterated over and unlocked, which actually aids in the first point of this commit.
2024-05-11 02:17:11 -07:00
David Rubin
5e010b6dea riscv: reorganize binOp and implement cmp_imm_gte MIR
this was an annoying one to do, as there is no (to my knowledge) myriad sequence
that will allow us to do `gte` compares with an immediate without allocating a register.
RISC-V provides a single instruction to do compares, that being `lt`, and so you need to
use more than one for other variants, but in this case, i believe you need to allocate a register.
2024-05-11 02:17:11 -07:00