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link/macho: print error message when hitting unexpected remainder error
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@ -660,6 +660,19 @@ fn resolveRelocInner(
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// Address of the __got_zig table entry if any.
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const ZIG_GOT = @as(i64, @intCast(rel.getZigGotTargetAddress(macho_file)));
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const divExact = struct {
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fn divExact(atom: Atom, r: Relocation, num: u12, den: u12, ctx: *MachO) !u12 {
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return math.divExact(u12, num, den) catch {
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try ctx.reportParseError2(atom.getFile(ctx).getIndex(), "{s}: unexpected remainder when resolving {s} at offset 0x{x}", .{
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atom.getName(ctx),
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r.fmtPretty(ctx.getTarget().cpu.arch),
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r.offset,
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});
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return error.UnexpectedRemainder;
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};
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}
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}.divExact;
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switch (rel.tag) {
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.local => relocs_log.debug(" {x}<+{d}>: {s}: [=> {x}] atom({d})", .{
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P,
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@ -831,12 +844,12 @@ fn resolveRelocInner(
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};
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inst.load_store_register.offset = switch (inst.load_store_register.size) {
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0 => if (inst.load_store_register.v == 1)
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try math.divExact(u12, @truncate(target), 16)
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try divExact(self, rel, @truncate(target), 16, macho_file)
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else
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@truncate(target),
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1 => try math.divExact(u12, @truncate(target), 2),
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2 => try math.divExact(u12, @truncate(target), 4),
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3 => try math.divExact(u12, @truncate(target), 8),
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1 => try divExact(self, rel, @truncate(target), 2, macho_file),
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2 => try divExact(self, rel, @truncate(target), 4, macho_file),
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3 => try divExact(self, rel, @truncate(target), 8, macho_file),
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};
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try writer.writeInt(u32, inst.toU32(), .little);
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}
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@ -847,7 +860,7 @@ fn resolveRelocInner(
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assert(rel.meta.length == 2);
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assert(!rel.meta.pcrel);
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const target = math.cast(u64, G + A) orelse return error.Overflow;
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aarch64.writeLoadStoreRegInst(try math.divExact(u12, @truncate(target), 8), code[rel_offset..][0..4]);
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aarch64.writeLoadStoreRegInst(try divExact(self, rel, @truncate(target), 8, macho_file), code[rel_offset..][0..4]);
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},
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.tlvp_pageoff => {
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@ -899,7 +912,7 @@ fn resolveRelocInner(
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.load_store_register = .{
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.rt = reg_info.rd,
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.rn = reg_info.rn,
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.offset = try math.divExact(u12, @truncate(target), 8),
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.offset = try divExact(self, rel, @truncate(target), 8, macho_file),
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.opc = 0b01,
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.op1 = 0b01,
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.v = 0,
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@ -60,6 +60,59 @@ pub fn lessThan(ctx: void, lhs: Relocation, rhs: Relocation) bool {
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return lhs.offset < rhs.offset;
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}
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const FormatCtx = struct { Relocation, std.Target.Cpu.Arch };
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pub fn fmtPretty(rel: Relocation, cpu_arch: std.Target.Cpu.Arch) std.fmt.Formatter(formatPretty) {
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return .{ .data = .{ rel, cpu_arch } };
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}
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fn formatPretty(
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ctx: FormatCtx,
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comptime unused_fmt_string: []const u8,
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options: std.fmt.FormatOptions,
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writer: anytype,
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) !void {
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_ = options;
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_ = unused_fmt_string;
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const rel, const cpu_arch = ctx;
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const str = switch (rel.type) {
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.signed => "X86_64_RELOC_SIGNED",
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.signed1 => "X86_64_RELOC_SIGNED_1",
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.signed2 => "X86_64_RELOC_SIGNED_2",
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.signed4 => "X86_64_RELOC_SIGNED_4",
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.got_load => "X86_64_RELOC_GOT_LOAD",
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.tlv => "X86_64_RELOC_TLV",
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.zig_got_load => "ZIG_GOT_LOAD",
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.page => "ARM64_RELOC_PAGE21",
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.pageoff => "ARM64_RELOC_PAGEOFF12",
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.got_load_page => "ARM64_RELOC_GOT_LOAD_PAGE21",
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.got_load_pageoff => "ARM64_RELOC_GOT_LOAD_PAGEOFF12",
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.tlvp_page => "ARM64_RELOC_TLVP_LOAD_PAGE21",
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.tlvp_pageoff => "ARM64_RELOC_TLVP_LOAD_PAGEOFF12",
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.branch => switch (cpu_arch) {
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.x86_64 => "X86_64_RELOC_BRANCH",
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.aarch64 => "ARM64_RELOC_BRANCH26",
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else => unreachable,
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},
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.got => switch (cpu_arch) {
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.x86_64 => "X86_64_RELOC_GOT",
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.aarch64 => "ARM64_RELOC_POINTER_TO_GOT",
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else => unreachable,
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},
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.subtractor => switch (cpu_arch) {
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.x86_64 => "X86_64_RELOC_SUBTRACTOR",
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.aarch64 => "ARM64_RELOC_SUBTRACTOR",
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else => unreachable,
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},
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.unsigned => switch (cpu_arch) {
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.x86_64 => "X86_64_RELOC_UNSIGNED",
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.aarch64 => "ARM64_RELOC_UNSIGNED",
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else => unreachable,
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},
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};
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try writer.writeAll(str);
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}
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pub const Type = enum {
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// x86_64
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/// RIP-relative displacement (X86_64_RELOC_SIGNED)
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