564 Commits

Author SHA1 Message Date
Luuk de Gram
be08d2bdbd
wasm: Fix unreachable paths
When the last instruction is a debug instruction, the type of it is void.
Similarly for 'noreturn' emit an 'unreachable' instruction to tell the wasm-validator
the path cannot be reached.

Also respect the '--strip' flag in the self-hosted wasm linker and not emit a 'name' section
when the flag is set to `true`.
2022-04-19 19:58:49 +02:00
joachimschmidt557
3bfb1616db stage2 ARM: move genArgDbgInfo back to CodeGen
This removes the questionable Air -> Mir dependency that existed
before. The x86_64 backend also performed this change.
2022-04-16 09:41:27 +02:00
Andrew Kelley
4c83b11f71
Merge pull request #11438 from Vexu/stage2-fixes
Stage2 fixes
2022-04-15 12:02:55 -04:00
Jakub Konka
52c8ac1a84 stage2: lower u128, and refactor some bits in x64 2022-04-15 11:50:08 -04:00
Veikka Tuominen
6ad510d832 update self hosted sources to language changes 2022-04-15 11:17:19 +03:00
Jakub Konka
2635e4ca6e
Merge pull request #11434 from koachan/sparc64-codegen 2022-04-14 21:38:35 +02:00
Andrew Kelley
2587474717 stage2: progress towards stage3
* The `@bitCast` workaround is removed in favor of `@ptrCast` properly
   doing element casting for slice element types. This required an
   enhancement both to stage1 and stage2.
 * stage1 incorrectly accepts `.{}` instead of `{}`. stage2 code that
   abused this is fixed.
 * Make some parameters comptime to support functions in switch
   expressions (as opposed to making them function pointers).
 * Avoid relying on local temporaries being mutable.
 * Workarounds for when stage1 and stage2 disagree on function pointer
   types.
 * Workaround recursive formatting bug with a `@panic("TODO")`.
 * Remove unreachable `else` prongs for some inferred error sets.

All in effort towards #89.
2022-04-14 10:12:45 -07:00
Koakuma
c07213269f stage2: zig fmt 2022-04-14 23:26:03 +07:00
Koakuma
9201fbe85b stage2: sparcv9: Add cmp_lt_errors_len AIR inst & fix asm parsing 2022-04-14 22:34:51 +07:00
Koakuma
b916ba18b6 stage2: sparcv9: Fix Tcc encoding 2022-04-14 22:18:06 +07:00
Koakuma
dcb12a7941 stage2: sparcv9: Use regular structs to encode instructions
Currently packed structs still has endian-dependent behavior, so it results
in code that is not portable across platforms (see also issue 10113).
2022-04-14 22:18:06 +07:00
Koakuma
1467590e40 stage2: sparcv9: Implement enough instruction to compile simple exes 2022-04-14 22:18:06 +07:00
Koakuma
cfd389f927 stage2: sparcv9: zig fmt 2022-04-14 22:18:06 +07:00
Flandre Scarlet
ab2ea9fb09 stage2: sparcv9: Test failure error logging 2022-04-14 22:18:06 +07:00
Koakuma
7051970ad7 stage2: sparcv9: implement basic instruction lowering 2022-04-14 22:18:06 +07:00
Koakuma
5e2045cbe5 stage2: sparcv9: Implement basic asm codegen 2022-04-14 22:18:06 +07:00
Koakuma
42f4bd3421 stage2: sparcv9: Add breakpoint, ret, and calling mechanism 2022-04-14 22:18:06 +07:00
Koakuma
1972a2b080 stage2: sparcv9: Add placeholders to generate a minimal program 2022-04-14 22:18:06 +07:00
Koakuma
cec48f2cf1 stage2: sparcv9: Different formatting for genBody 2022-04-14 22:18:06 +07:00
Koakuma
5ab6b5a777 stage2: sparcv9: implement dbgAdvancePCAndLine 2022-04-14 22:18:06 +07:00
Koakuma
71cd3466ec stage2: sparcv9: Adjust RegisterManager settings 2022-04-14 22:18:06 +07:00
Koakuma
18c98eb429 stage2: sparcv9: Placeholder for Air instructions in genBody 2022-04-14 22:18:06 +07:00
Koakuma
94d70bdb69 stage2: sparcv9: Change ordering in Mir Tag 2022-04-14 22:18:05 +07:00
Koakuma
94a84e783e stage2: sparcv9: Implement basic prologue/epilogue Mir emission 2022-04-14 22:18:05 +07:00
Koakuma
927706e6d0 stage2: sparcv9: Emit debug inst placeholder 2022-04-14 22:18:05 +07:00
Koakuma
cf13356dab stage2: sparcv9: Mir extraData implementation 2022-04-14 22:18:05 +07:00
Koakuma
1ba5227216 stage2: sparcv9: Initial resolveCallingConventionValues implementation 2022-04-14 22:18:05 +07:00
Koakuma
a5a89fde13 stage2: sparcv9: Add skeleton codegen impl and necessary fields 2022-04-14 22:18:05 +07:00
Koakuma
a30688ef2a stage2: sparcv9: Add some initial checks in codegen 2022-04-14 22:18:05 +07:00
Jakub Konka
edb428fae4 macho,x64: resolve debug info relocs for RIP-based addressing
Sometimes we will want to generate debug info for a constant that
has been lowered to memory and not copied anywhere else. For this
we will need to defer resolution on PIE platforms until all locals
(including GOT entries) have been allocated.
2022-04-13 19:50:23 +02:00
Jakub Konka
3f912430bd stage2,x64: deref memory if referenced via GOT for local vars 2022-04-13 16:24:56 +02:00
Jakub Konka
4c50a27d68 stage2,x64: generate debug info for local vars at hardcoded mem addr 2022-04-13 14:31:04 +02:00
Jakub Konka
baeff1762b stage2,x64: recursively mark decls as alive when lowering 2022-04-13 13:52:01 +02:00
Andrew Kelley
b0edd8752a Liveness: modify encoding to support over 32 operands
Prior to this, Liveness encoded `asm`, `call`, and `aggregate_init` with
a single 32-bit integer, allowing up to 35 operands (3 are provided by
the regular tomb_bits). However, the Zig language allows function calls
with more than 35 arguments, inline assembly with more than 35 inputs,
and anonymous tuples with more than 35 elements.

The new encoding stores an index to the extra array instead of the bits
directly, and then as many extra elements as needed to encode all the
operands. The MSB is used as a flag to tell which element is the last
one, allowing for 31 bits per element.

Prior to this, print_air did not bother correctly printing tombstones
for these instructions; now it does.

In addition to updating the BigTomb iteration logic in the machine code
backends, this commit extracts the common logic into the Liveness namespace.
2022-04-12 11:22:12 -07:00
Andrew Kelley
6ae8fe193b Liveness: utilize Air.refToIndex 2022-04-07 23:19:19 -07:00
Luuk de Gram
ac873367b9 wasm: Use 'select' instruction for max/min
Rather than using blocks and control flow to check which operand is the maximum or minimum,
we use wasm's `select` instruction which returns us the operand based on a result from a comparison.
This saves us the need of control flow, as well as reduce the instruction count from 13 to 7.
2022-04-05 21:56:25 +02:00
Damien Firmenich
5fafcc2b62
zig fmt: remove trailing whitespace on doc comments
Fixes #11353

The renderer treats comments and doc comments differently since doc
comments are parsed into the Ast. This commit adds a check after getting
the text for the doc comment and trims whitespace at the end before
rendering.

The `a = 0,` in the test is here to avoid a ParseError while parsing the
test.
2022-04-05 18:08:33 +03:00
Jakub Konka
364e53f3bf dwarf: emit debug info for local variables on x86_64
Add support for emitting debug info for local variables within a subprogram.
This required moving bits responsible for populating the debug info back to
`CodeGen` from `Emit` as we require the operand to be resolved at callsite
plus we need to know its type. Without enforcing this, we could end up
with a `dead` mcv.
2022-04-04 21:46:53 +02:00
Luuk de Gram
2c40b37f79 wasm: Implement @ctz for bitsize <= 64
Implements the `ctz` AIR instruction for integers with bitsize <= 64.
When the bitsize of the integer does not match the bitsize of a wasm type,
we first XOR the value with the value of (1<<bitsize) to set the right bits
and ensure we will only count the trailing zeroes of the integer with the correct bitsize.
2022-04-02 21:54:01 +02:00
Luuk de Gram
bd27fe2bf5 wasm: Implement @clz
Implements the `clz` AIR instruction for integers with bitsize <= 64.
When the bitsize of the integer is not the same as wasm's bitsize,
we substract the difference in bits as those will always be 0 for the integer, but should
not be counted towards the end result. We also wrap the result to ensure it fits
in the result type as documented in the language reference.
2022-04-02 21:54:01 +02:00
Luuk de Gram
5ba03369ee wasm: Implement @mulAdd for f32, f64
This implements the `mul_add` AIR instruction for floats of bitsize 32 and 64.
f16's will require us being able to extend and truncate f16's to correctly
store and load them without losing the accuracy.
2022-04-02 21:54:01 +02:00
Luuk de Gram
219fa192c6 wasm: Implement @maximum & @minimum
This implements the `max` and `min` AIR instructions by checking
whether LHS is great/lesser than RHS. If that's the case, we assign
LHS to the result, otherwise assign RHS to it instead.
2022-04-02 21:54:01 +02:00
joachimschmidt557
8c12ad98b8
stage2 ARM: implement mul_with_overflow for ints <= 32 bits 2022-04-01 22:51:18 +02:00
joachimschmidt557
c4778fc029
stage2 ARM: implement mul_with_overflow for ints <= 16 bits 2022-04-01 22:02:56 +02:00
joachimschmidt557
77e70189f4
stage2 ARM: implement shl_with_overflow for ints <= 32 bits 2022-04-01 22:02:56 +02:00
joachimschmidt557
37a8c28802
stage2 ARM: implement add/sub_with_overflow for ints < 32 bits 2022-04-01 22:02:56 +02:00
joachimschmidt557
7285f0557c
stage2 ARM: implement add/sub_with_overflow for u32/i32 2022-04-01 22:02:55 +02:00
joachimschmidt557
e2e69803dc
stage2 ARM: change binOp lowering mechanism to use Mir tags
The Air -> Mir correspondence is not 1:1, so this better represents
what Mir insruction we actually want to generate.
2022-04-01 22:02:51 +02:00
Jakub Konka
fd29ddc06c x64: implement add/sub with wrapping and xor op 2022-04-01 11:37:18 +02:00
Veikka Tuominen
75c2cff40e stage2: handle assembly input names 2022-03-31 01:33:28 -04:00