Jakub Konka
5195b87639
Merge pull request #11396 from wojtekmach/wm-zig-cc-subsystem
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zig cc: support --subsystem linker flag
2022-04-18 19:20:23 +02:00
Wojtek Mach
b2344cc18e
Support --subsystem=x instead of --subsystem,x
2022-04-18 11:43:17 +02:00
Andrew Kelley
a7c05c06be
stage2: expose progress bar API to linker backends
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This gives us insight as to what is happening when we are waiting for
things such as LLVM emit object and LLD linking.
2022-04-17 04:09:35 -07:00
Jakub Konka
8f75823728
Merge pull request #11446 from ziglang/aarch64-macos-llvm
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stage2: fix behavior test failures on aarch64-macos (LLVM+native), and other minor fixes
2022-04-16 18:07:02 +02:00
Jakub Konka
897df18573
stage2: fix @mulAdd on aarch64 Darwin
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According to Apple docs, the long double type is a double precision
IEEE754 binary floating-point type, which makes it identical to the
double type. This behavior contrasts to the standard specification,
in which a long double is a quad-precision, IEEE754 binary,
floating-point type.
Thus, we need to take this into account when using the compiler
intrinsics so that we select the correct function version for
FloatMulAdd.
2022-04-16 12:23:47 +02:00
Jakub Konka
88d87d6506
stage2,macho: swap out inodes before checking for intermediary basename
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This way we avoid the infamous SIGKILL on arm64 macos.
2022-04-16 12:06:58 +02:00
Andrew Kelley
578a792b33
Merge pull request #11442 from Vexu/stage3
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Make self hosted compiler capable of building itself
2022-04-16 05:42:25 -04:00
joachimschmidt557
3bfb1616db
stage2 ARM: move genArgDbgInfo back to CodeGen
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This removes the questionable Air -> Mir dependency that existed
before. The x86_64 backend also performed this change.
2022-04-16 09:41:27 +02:00
Veikka Tuominen
101aac92c2
stage2: fix bugs preventing stage2 from building stage3 with LLVM
2022-04-15 23:32:26 +03:00
Veikka Tuominen
1c4c826a50
AstGen: fix defer generation in breakExpr
2022-04-15 22:33:07 +03:00
Veikka Tuominen
7be62f695f
stage2 llvm: fix optional pointers to zero bit payloads
2022-04-15 19:17:50 +03:00
Andrew Kelley
4c83b11f71
Merge pull request #11438 from Vexu/stage2-fixes
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Stage2 fixes
2022-04-15 12:02:55 -04:00
Jakub Konka
52c8ac1a84
stage2: lower u128, and refactor some bits in x64
2022-04-15 11:50:08 -04:00
Veikka Tuominen
dbe0d3d579
stage2 llvm: handle dollar signs in asm template
2022-04-15 16:16:22 +03:00
Veikka Tuominen
ef7282bab4
stage2 macho: workaround stage2 bugs
2022-04-15 16:05:27 +03:00
Veikka Tuominen
3723eb7f31
Merge pull request #11242 from schmee/sema-handle-more-union-errors
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stage2: add more union compile errors / improve error messages
2022-04-15 11:34:04 +03:00
Veikka Tuominen
6ad510d832
update self hosted sources to language changes
2022-04-15 11:17:19 +03:00
Veikka Tuominen
4911d39769
AstGen: handle rl_ty_inst for mutable variables
2022-04-15 11:17:06 +03:00
Veikka Tuominen
4ef1c1c705
Sema: allow fieldType on optionals and error unions
2022-04-15 10:24:18 +03:00
Luuk de Gram
d66c61a2cf
wasm-linker: Prevent overalignment for segments
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Previously, the data segments were being aligned twice.
This caused us to overalign the segment and therefore allocate a much larger
size for each segment than was required. This fix ensures we align and set the size
just once, ensuring semantically correct binaries as well as smaller binaries.
2022-04-14 22:53:13 +02:00
Luuk de Gram
cf37101108
wasm-linker: Add function table indexes
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When linking with an object file, verify if a relocation is a table index relocation.
If that's the case, add the relocation target to the function table.
2022-04-14 22:53:13 +02:00
Luuk de Gram
321a164269
wasm-linker: Fix memory leak
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This fixes a memory leak when an object file contains one or more element sections which
then contains one or more function indexes. This commit ensures the slice of index functions
for each element section will be freed upon resource deallocation also.
2022-04-14 22:53:13 +02:00
Jakub Konka
2635e4ca6e
Merge pull request #11434 from koachan/sparc64-codegen
2022-04-14 21:38:35 +02:00
Jakub Konka
35171dd3db
Merge pull request #11433 from ziglang/elf-fixes
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elf: support `--strip` option and set symtab size when writing globals
2022-04-14 20:04:29 +02:00
Andrew Kelley
2587474717
stage2: progress towards stage3
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* The `@bitCast` workaround is removed in favor of `@ptrCast` properly
doing element casting for slice element types. This required an
enhancement both to stage1 and stage2.
* stage1 incorrectly accepts `.{}` instead of `{}`. stage2 code that
abused this is fixed.
* Make some parameters comptime to support functions in switch
expressions (as opposed to making them function pointers).
* Avoid relying on local temporaries being mutable.
* Workarounds for when stage1 and stage2 disagree on function pointer
types.
* Workaround recursive formatting bug with a `@panic("TODO")`.
* Remove unreachable `else` prongs for some inferred error sets.
All in effort towards #89 .
2022-04-14 10:12:45 -07:00
Koakuma
c07213269f
stage2: zig fmt
2022-04-14 23:26:03 +07:00
Koakuma
9201fbe85b
stage2: sparcv9: Add cmp_lt_errors_len AIR inst & fix asm parsing
2022-04-14 22:34:51 +07:00
Koakuma
47b136e3b3
stage2: Add SPARC function alignment
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This is based on @kubkon's suggestion.
2022-04-14 22:18:06 +07:00
Koakuma
a6ce2fc3dc
linker: ELF: Add page sizes for ppc64le and sparcv9
2022-04-14 22:18:06 +07:00
Koakuma
b916ba18b6
stage2: sparcv9: Fix Tcc encoding
2022-04-14 22:18:06 +07:00
Koakuma
dcb12a7941
stage2: sparcv9: Use regular structs to encode instructions
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Currently packed structs still has endian-dependent behavior, so it results
in code that is not portable across platforms (see also issue 10113).
2022-04-14 22:18:06 +07:00
Koakuma
1467590e40
stage2: sparcv9: Implement enough instruction to compile simple exes
2022-04-14 22:18:06 +07:00
Koakuma
1f63afa7c9
stage2: sparcv9: Register the backend in stdlib & driver
2022-04-14 22:18:06 +07:00
Koakuma
cfd389f927
stage2: sparcv9: zig fmt
2022-04-14 22:18:06 +07:00
Flandre Scarlet
ab2ea9fb09
stage2: sparcv9: Test failure error logging
2022-04-14 22:18:06 +07:00
Koakuma
7051970ad7
stage2: sparcv9: implement basic instruction lowering
2022-04-14 22:18:06 +07:00
Koakuma
5e2045cbe5
stage2: sparcv9: Implement basic asm codegen
2022-04-14 22:18:06 +07:00
Koakuma
42f4bd3421
stage2: sparcv9: Add breakpoint, ret, and calling mechanism
2022-04-14 22:18:06 +07:00
Koakuma
1972a2b080
stage2: sparcv9: Add placeholders to generate a minimal program
2022-04-14 22:18:06 +07:00
Koakuma
cec48f2cf1
stage2: sparcv9: Different formatting for genBody
2022-04-14 22:18:06 +07:00
Koakuma
5ab6b5a777
stage2: sparcv9: implement dbgAdvancePCAndLine
2022-04-14 22:18:06 +07:00
Koakuma
71cd3466ec
stage2: sparcv9: Adjust RegisterManager settings
2022-04-14 22:18:06 +07:00
Koakuma
18c98eb429
stage2: sparcv9: Placeholder for Air instructions in genBody
2022-04-14 22:18:06 +07:00
Koakuma
94d70bdb69
stage2: sparcv9: Change ordering in Mir Tag
2022-04-14 22:18:05 +07:00
Koakuma
94a84e783e
stage2: sparcv9: Implement basic prologue/epilogue Mir emission
2022-04-14 22:18:05 +07:00
Koakuma
927706e6d0
stage2: sparcv9: Emit debug inst placeholder
2022-04-14 22:18:05 +07:00
Koakuma
cf13356dab
stage2: sparcv9: Mir extraData implementation
2022-04-14 22:18:05 +07:00
Koakuma
1ba5227216
stage2: sparcv9: Initial resolveCallingConventionValues implementation
2022-04-14 22:18:05 +07:00
Koakuma
a5a89fde13
stage2: sparcv9: Add skeleton codegen impl and necessary fields
2022-04-14 22:18:05 +07:00
Koakuma
a30688ef2a
stage2: sparcv9: Add some initial checks in codegen
2022-04-14 22:18:05 +07:00
