8812 Commits

Author SHA1 Message Date
Luuk de Gram
3a059ebe4c wasm: Fixes for error union semantics 2022-05-24 15:34:52 -07:00
Luuk de Gram
c90a97f9be codegen: Order error union fields per alignment
Based on the size of the payload the native backends will lower
the error union with its fields (errorset & payload) in the correct order.
e.g. ErrorA!u8 will first lower the error set's value and then the payload.
In the event of ErrorA!u32 will lower the payload first.
2022-05-24 15:34:52 -07:00
Andrew Kelley
3264abe3d8 stage2: fixes for error union semantics
* Sema: avoid unnecessary safety checks when an error set is empty.
 * Sema: make zirErrorToInt handle comptime errors that are represented
   as integers.
 * Sema: make empty error sets properly integrate with
   typeHasOnePossibleValue.
 * Type: correct the ABI alignment and size of error unions which have
   both zero-bit error set and zero-bit payload. The previous code did
   not account for the fact that we still need to store a bit for
   whether there is an error.
 * LLVM: lower error unions possibly with the payload first or with the
   error code first, depending on alignment. Previously it always put
   the error code first and used a padding array.
 * LLVM: lower functions which have an empty error set as the return
   type the same as anyerror, so that they can be used where
   fn()anyerror function pointers are expected. In such functions, Zig
   will lower ret to returning zero instead of void.

As a result, one more behavior test is passing.
2022-05-24 15:34:52 -07:00
Andrew Kelley
818fbd9c56 stage2: string literal interning
This is a temporary addition to stage2 in order to match stage1 behavior,
however the end-game once the lang spec is settled will be to use a global
InternPool for comptime memoized objects, making this behavior consistent
across all types, not only string literals. Or, we might decide to not
guarantee string literals to have equal comptime pointers, in which case
this commit can be reverted.
2022-05-24 01:01:24 -07:00
Thomas Cheng
64de32b341 Fix segfault in error note 2022-05-23 11:57:30 +03:00
Andrew Kelley
b64a1d5abb
Merge pull request #11684 from ziglang/fix-10318
Set macOS/iPhoneOS/tvOS/watchOS ABI to none (unspecified) by default
2022-05-22 19:29:42 -04:00
Jakub Konka
cbefd354a6 Bump support macOS versions; clean up allocs in llvm.targetTriple 2022-05-22 22:31:41 +02:00
joachimschmidt557
b56b4428a3 stage2 ARM: fix recursive fibonacci
Some handling of register_c_flag/register_v_flag was incorrect.
2022-05-22 21:02:32 +02:00
Jakub Konka
e306d04473 Return an error when macOS ABI is not {none, simulator, macabi} 2022-05-22 17:45:07 +02:00
Jakub Konka
f8a1a2c4a1 stage2: append min version to target triple when lowering to LLVM 2022-05-22 17:45:07 +02:00
Jakub Konka
5b813f1a2a Set macOS/iPhoneOS/tvOS/watchOS ABI to none (unspecified) by default
Prior to this change we would assume the ABI for Apple targets to
be GNU which could result in subtle errors in LLVM emitting calls
to non-existent system libc provided functions such as `_sincosf`
which is a GNU extension and as such is not provided by macOS for example.
This would result in linker errors where the linker would not be
able to find the said symbol in `libSystem.tbd`.

With this change, we now correctly identify macOS (and other Apple
platforms) as having ABI `unknown` which translates to unspecified
in LLVM under-the-hood:

```
// main.ll
target triple = "aarch64-unknown-macos-unknown"
```

Note however that we never suffix the target OS with target version
such as `macos11` or `macos12` which means we fail to instruct LLVM
of potential optimisations provided by the OS such as the availability
of function `___sincosf_stret`. I suggest we investigate that in a
follow-up commit.
2022-05-22 17:45:02 +02:00
joachimschmidt557
9747303d16 stage2 ARM: Introduce MCValue.cpsr_flags
MCValue.cpsr_flags replaces
MCValue.compare_flags_{signed,unsigned}. This simplifies a lot of
stuff and enables an MCValue to represent only the overflow bits in
the CPU (previously, it was only possible to represent a register +
the overflow bits).
2022-05-21 22:15:04 +02:00
Andrew Kelley
1f5b0c1156
Merge pull request #11689 from ziglang/llvm-cc
LLVM: rework calling convention lowering
2022-05-21 15:22:52 -04:00
Andrew Kelley
f31f86a86a LLVM: fix calling convention lowering involving pointers
The previous commit caused LLVM module verification failure because we
attemped to bitcast LLVM pointers to i64 parameters. This is exactly
what we want, however it's technically not allowed according to LLVM's
type system. It could have been fixed trivially by using ptrtoint
instead of bitcast in the case of pointers, however, out of concern for
inttoptr being problematic for the optimizer, I put in special code to
detect when a given parameter can be treated as its actual type rather
than an integer type. This makes Zig's output LLVM IR closer to what
Clang outputs.
2022-05-21 00:09:30 -07:00
Jakub Konka
800edb03b5 regalloc: test allocating from multiple register claases 2022-05-21 08:40:47 +02:00
Andrew Kelley
1697a6f044 LLVM: rework calling convention lowering
The previous implementation of calling conventions was hacky and broken.
This commit reworks lowerFnParamTy into iterateParamTypes which returns
enum tags indicating how to handle each parameter. This is then used in
the three places that matter:
 * lowering a function type to llvm type
 * converting function parameters to the canonical type representation
   (with respect to isByRef).
 * converting canonical type representation to function arguments at
   callsites (again with respect to isByRef).

As a result, we are one step closer to the C ABI tests passing. Before
this commit, attempting to build them crashed the compiler. I isolated
the broken function and verified that it now is lowered correctly. I
will keep working on this one piece at a time until all the C ABI tests
pass, and then I will enable all of them in the CI.
2022-05-20 21:50:23 -07:00
Andrew Kelley
1a92264b3d
Merge pull request #11671 from ziglang/stage2-behavior
stage2 bug fixes aimed towards more behavior tests passing
2022-05-20 18:35:19 -04:00
Jakub Konka
704d38ba49
Merge pull request #11681 from ziglang/x64-floats-tmp
x64: add prelim support for SSE/AVX-based floating-point ops
2022-05-20 17:19:28 +02:00
Jakub Konka
274654d73e x64: implement matching SSE instructions for generic cross-comp target 2022-05-20 13:52:52 +02:00
Andrew Kelley
fcd4efd8ec Sema: introduce laziness to @sizeOf
Motivation: the behavior test that is now passing.

The main change in this commit is introducing `Type.abiSizeAdvanced`,
`Value.Tag.lazy_size`, and adjusting `Sema.zirSizeOf` to take advantage
of these.

However, the bulk of lines changed in this commit ended up being moving
logic from value.zig and type.zig into Sema.zig. This logic had no
business being in Type/Value as it was only called from a Sema context,
and we need access to the Sema context for error reporting when a lazy
Value is resolved.

Also worth mentioning is that I bumped up the comptime `@floatToInt`
implementation from using f64 to f128.
2022-05-20 02:47:20 -07:00
Andrew Kelley
cd04b49041 stage2: fix @call when used in a comptime or nosuspend block
`@call` allows specifying the modifier explicitly, however it can still
appear in a context that overrides the modifier. This commit adds flags
to the BuiltinCall ZIR encoding. Since we have unused bits I also threw
in the ensure_result_used mechanism.

I also deleted a behavior test that was checking for bound function
behavior where I think stage2 behavior is correct and stage1 behavior
is incorrect.
2022-05-20 02:47:20 -07:00
Andrew Kelley
5626bb45d2 Sema: fix comptime @floatCast downcast 2022-05-20 02:47:20 -07:00
Ali Chraghi
58943fc627 wasm-linker: add -mwasm64 linker parameter for wasm64 target 2022-05-20 08:26:41 +02:00
Jakub Konka
0e43d007c0 regalloc: temporarily nerf back to raw ints until stage2 catches up 2022-05-20 07:36:15 +02:00
Motiejus Jakštys
1d532f12b5 [Elf] add -z nocopyreloc
Warnings about non-implemented `-z nocopyreloc` are common when
compiling go code (including Go's tests themselves). Let's just
make it stop complaining.
2022-05-19 20:21:07 -04:00
Jakub Konka
e95dfac03e regalloc: make register class bitmask non-optional 2022-05-19 23:54:48 +02:00
Jakub Konka
f766b25f82 x64: load float from memory to register on PIE targets 2022-05-19 20:24:06 +02:00
Jakub Konka
5cbfd5819e x64: check for floating-point intrinsics in codegen 2022-05-19 19:39:34 +02:00
Jakub Konka
283f40e4e9 x64: use StaticBitSet instead of an integer internally in RegisterManager 2022-05-19 19:39:34 +02:00
Jakub Konka
080d138b9d x64: re-enable incremental tests 2022-05-19 19:39:34 +02:00
Jakub Konka
6d32498c55 x64: re-enable behavior tests 2022-05-19 19:39:34 +02:00
Jakub Konka
36b939e8db x64: handle basic f32 using AVX registers 2022-05-19 19:39:34 +02:00
Jakub Konka
020f99d893 x64: remove special-casing of AVX for br() 2022-05-19 19:39:34 +02:00
Jakub Konka
f346150820 x64: use register classes mask to select between gp and avx 2022-05-19 19:39:34 +02:00
Jakub Konka
549174f743 regalloc: allow for optional selector mask when allocating 2022-05-19 19:39:32 +02:00
Jakub Konka
9e5c8cb008 x64: merge general purpose with simd register into one bitset
This way, we do not have to tweak the `RegisterManager` to handle
multiple register types - we have one linear space instead. Additionally
we can use the bitset itself to separate the registers into overlapping
(the ones that are aliases of differing bitwidths) and nonoverlapping
classes (for example, AVX registers do not overlap general purpose
registers, thus they can be allocated simultaneously).

Another huge benefit of this simple approach is the fact that we can
still refer to *all* registers regardless of their class via enum
literals which makes the code so much more readable.

Finally, `RegisterLock` is universal across different register classes.
2022-05-19 19:37:29 +02:00
Jakub Konka
2aee230251 x64: add unordered cmp with EFLAGS 2022-05-19 19:37:28 +02:00
Jakub Konka
357561840d x64: load/store to/from AVX registers for f64 2022-05-19 19:36:35 +02:00
Jakub Konka
0835486249 x64: add vmovsd RM and MR lowerings (first draft) 2022-05-19 19:36:35 +02:00
Jakub Konka
019cc94ec7 x64: clean up populating VEX prefix 2022-05-19 19:36:35 +02:00
Jakub Konka
875a16030c x64: extend Emit to allow for AVX registers 2022-05-19 19:36:35 +02:00
Jakub Konka
70d809e0bb x64: add AVX registers and Vex prefix sub-encoder 2022-05-19 19:36:35 +02:00
Andrew Kelley
50a5ddecc5
Merge pull request #11635 from wsengir/stage2-errsetcast-safety
stage2: `@errSetCast` safety
2022-05-18 16:35:37 -04:00
Andrew Kelley
9031cc54f2 Sema: implement @intCast for vectors 2022-05-17 23:50:38 -07:00
Andrew Kelley
b6798c26ef stage2: fix pointer arithmetic result type
This makes it so the result of doing pointer arithmetic creates a new
pointer type that has adjusted alignment.
2022-05-17 23:50:38 -07:00
Andrew Kelley
00f3d84f38 LLVM: support mixing extern and export with the same symbol name 2022-05-17 23:50:38 -07:00
Luuk de Gram
ed25ce77f5 wasm: Implement {add/sub}WithOverflow for 128bit 2022-05-18 07:43:33 +02:00
Luuk de Gram
fd081c74f1 wasm: Support not instruction for 128 bit integers
This also fixes the instruction for all other integer bitsizes,
as it was previously assuming to always be a bool.

128 bit substraction was also fixed as it contained a bug where it swapped
lhs with rhs.
2022-05-18 07:43:33 +02:00
Luuk de Gram
10fe24c043 wasm: Implement trunc/wrap for 128 bit integers
This also implments wrapping for arbitrary integer widths between 64 and 128.
`@truncate` was fixed where the wasm types between operand and result differentiated.
We solved this by first casting and then wrapping.
2022-05-18 07:43:33 +02:00
Luuk de Gram
ea073a6b76 wasm: Support 128bit integers for max/min/ctz/clz
`airMaxMin` was slightly updated to automatically support 128 bit integers,
by using the `cmp` function, instead of doing it manually. This makes the function
more maintanable as well.

`ctz` and `clz` now support 128 bit integers, while updating the previous implementation
also.
2022-05-18 07:43:33 +02:00