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x64: extend Emit to allow for AVX registers
This commit is contained in:
Jakub Konka
parent
70d809e0bb
commit
875a16030c
@ -25,7 +25,8 @@ const MCValue = @import("CodeGen.zig").MCValue;
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const Mir = @import("Mir.zig");
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const Module = @import("../../Module.zig");
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const Instruction = bits.Instruction;
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const Register = bits.Register;
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const GpRegister = bits.Register;
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const AvxRegister = bits.Register;
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const Type = @import("../../type.zig").Type;
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mir: Mir,
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@ -248,7 +249,7 @@ fn mirPushPop(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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switch (ops.flags) {
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0b00 => {
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// PUSH/POP reg
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return lowerToOEnc(tag, ops.reg1, emit.code);
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return lowerToOEnc(tag, .{ .register = ops.reg1 }, emit.code);
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},
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0b01 => {
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// PUSH/POP r/m64
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@ -271,6 +272,7 @@ fn mirPushPop(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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0b11 => unreachable,
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}
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}
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fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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@ -283,9 +285,9 @@ fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.I
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try lowerToMrEnc(.mov, RegisterOrMemory.mem(.qword_ptr, .{
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.disp = @bitCast(u32, -@intCast(i32, disp)),
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.base = ops.reg1,
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}), reg.to64(), emit.code);
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}), .{ .register = reg.to64() }, emit.code);
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} else {
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try lowerToRmEnc(.mov, reg.to64(), RegisterOrMemory.mem(.qword_ptr, .{
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try lowerToRmEnc(.mov, .{ .register = reg.to64() }, RegisterOrMemory.mem(.qword_ptr, .{
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.disp = @bitCast(u32, -@intCast(i32, disp)),
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.base = ops.reg1,
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}), emit.code);
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@ -319,7 +321,7 @@ fn mirJmpCall(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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return lowerToMEnc(tag, RegisterOrMemory.mem(ptr_size, .{ .disp = imm }), emit.code);
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}
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// JMP/CALL reg
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return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
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return lowerToMEnc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), emit.code);
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},
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0b10 => {
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// JMP/CALL r/m64
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@ -392,13 +394,13 @@ fn mirCondSetByte(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) Inne
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},
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else => unreachable,
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};
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return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1.to8()), emit.code);
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return lowerToMEnc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1.to8() }), emit.code);
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}
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fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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if (ops.flags == 0b00) {
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return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
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return lowerToRmEnc(tag, .{ .register = ops.reg1 }, RegisterOrMemory.reg(.{ .register = ops.reg2 }), emit.code);
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}
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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const ptr_size: Memory.PtrSize = switch (ops.flags) {
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@ -407,7 +409,7 @@ fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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0b10 => .dword_ptr,
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0b11 => .qword_ptr,
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};
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return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.mem(ptr_size, .{
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return lowerToRmEnc(tag, .{ .register = ops.reg1 }, RegisterOrMemory.mem(ptr_size, .{
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.disp = imm,
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.base = ops.reg2,
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}), emit.code);
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@ -428,10 +430,15 @@ fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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// I
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return lowerToIEnc(.@"test", imm, emit.code);
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}
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return lowerToMiEnc(.@"test", RegisterOrMemory.reg(ops.reg1), imm, emit.code);
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return lowerToMiEnc(.@"test", RegisterOrMemory.reg(.{ .register = ops.reg1 }), imm, emit.code);
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}
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// TEST r/m64, r64
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return lowerToMrEnc(.@"test", RegisterOrMemory.reg(ops.reg1), ops.reg2, emit.code);
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return lowerToMrEnc(
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.@"test",
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RegisterOrMemory.reg(.{ .register = ops.reg1 }),
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.{ .register = ops.reg2 },
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emit.code,
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);
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},
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else => return emit.fail("TODO more TEST alternatives", .{}),
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}
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@ -471,18 +478,18 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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// mov reg1, imm32
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// MI
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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return lowerToMiEnc(tag, RegisterOrMemory.reg(ops.reg1), imm, emit.code);
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return lowerToMiEnc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), imm, emit.code);
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}
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// mov reg1, reg2
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// RM
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return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
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return lowerToRmEnc(tag, .{ .register = ops.reg1 }, RegisterOrMemory.reg(.{ .register = ops.reg2 }), emit.code);
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},
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0b01 => {
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// mov reg1, [reg2 + imm32]
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// RM
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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const src_reg: ?Register = if (ops.reg2 == .none) null else ops.reg2;
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return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
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const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;
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return lowerToRmEnc(tag, .{ .register = ops.reg1 }, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
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.disp = imm,
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.base = src_reg,
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}), emit.code);
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@ -497,7 +504,7 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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return lowerToMrEnc(tag, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg2.size()), .{
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.disp = imm,
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.base = ops.reg1,
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}), ops.reg2, emit.code);
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}), .{ .register = ops.reg2 }, emit.code);
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},
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0b11 => {
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return emit.fail("TODO unused variant: mov reg1, reg2, 0b11", .{});
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@ -523,11 +530,16 @@ fn mirArithMemImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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}
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inline fn setRexWRegister(reg: Register) bool {
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if (reg.size() == 64) return true;
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return switch (reg) {
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.ah, .bh, .ch, .dh => true,
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else => false,
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};
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switch (reg) {
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.avx_register => return false,
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.register => |r| {
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if (r.size() == 64) return true;
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return switch (r) {
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.ah, .bh, .ch, .dh => true,
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else => false,
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};
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},
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}
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}
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inline fn immOpSize(u_imm: u32) u8 {
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@ -550,7 +562,7 @@ fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
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.scale = scale,
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.index = .rcx,
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};
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return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
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return lowerToRmEnc(tag, .{ .register = ops.reg1 }, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
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.disp = imm,
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.base = ops.reg2,
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.scale_index = scale_index,
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@ -578,7 +590,7 @@ fn mirArithScaleDst(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
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.disp = imm,
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.base = ops.reg1,
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.scale_index = scale_index,
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}), ops.reg2, emit.code);
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}), .{ .register = ops.reg2 }, emit.code);
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}
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fn mirArithScaleImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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@ -629,22 +641,27 @@ fn mirMovSignExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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switch (ops.flags) {
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0b00 => {
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const tag: Tag = if (ops.reg2.size() == 32) .movsxd else .movsx;
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return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
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return lowerToRmEnc(
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tag,
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.{ .register = ops.reg1 },
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RegisterOrMemory.reg(.{ .register = ops.reg2 }),
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emit.code,
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);
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},
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0b01 => {
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return lowerToRmEnc(.movsx, ops.reg1, RegisterOrMemory.mem(.byte_ptr, .{
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return lowerToRmEnc(.movsx, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.byte_ptr, .{
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.disp = imm,
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.base = ops.reg2,
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}), emit.code);
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},
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0b10 => {
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return lowerToRmEnc(.movsx, ops.reg1, RegisterOrMemory.mem(.word_ptr, .{
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return lowerToRmEnc(.movsx, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.word_ptr, .{
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.disp = imm,
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.base = ops.reg2,
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}), emit.code);
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},
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0b11 => {
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return lowerToRmEnc(.movsxd, ops.reg1, RegisterOrMemory.mem(.dword_ptr, .{
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return lowerToRmEnc(.movsxd, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.dword_ptr, .{
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.disp = imm,
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.base = ops.reg2,
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}), emit.code);
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@ -659,16 +676,21 @@ fn mirMovZeroExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const imm = if (ops.flags != 0b00) emit.mir.instructions.items(.data)[inst].imm else undefined;
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switch (ops.flags) {
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0b00 => {
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return lowerToRmEnc(.movzx, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
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return lowerToRmEnc(
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.movzx,
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.{ .register = ops.reg1 },
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RegisterOrMemory.reg(.{ .register = ops.reg2 }),
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emit.code,
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);
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},
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0b01 => {
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return lowerToRmEnc(.movzx, ops.reg1, RegisterOrMemory.mem(.byte_ptr, .{
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return lowerToRmEnc(.movzx, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.byte_ptr, .{
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.disp = imm,
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.base = ops.reg2,
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}), emit.code);
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},
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0b10 => {
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return lowerToRmEnc(.movzx, ops.reg1, RegisterOrMemory.mem(.word_ptr, .{
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return lowerToRmEnc(.movzx, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.word_ptr, .{
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.disp = imm,
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.base = ops.reg2,
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}), emit.code);
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@ -691,16 +713,16 @@ fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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if (ops.flags == 0b00) {
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// movabs reg, imm64
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// OI
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return lowerToOiEnc(.mov, ops.reg1, imm, emit.code);
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return lowerToOiEnc(.mov, .{ .register = ops.reg1 }, imm, emit.code);
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}
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if (ops.reg1 == .none) {
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// movabs moffs64, rax
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// TD
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return lowerToTdEnc(.mov, imm, ops.reg2, emit.code);
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return lowerToTdEnc(.mov, imm, .{ .register = ops.reg2 }, emit.code);
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}
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// movabs rax, moffs64
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// FD
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return lowerToFdEnc(.mov, ops.reg1, imm, emit.code);
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return lowerToFdEnc(.mov, .{ .register = ops.reg1 }, imm, emit.code);
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}
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fn mirFisttp(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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@ -751,18 +773,18 @@ fn mirShift(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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0b00 => {
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// sal reg1, 1
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// M1
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return lowerToM1Enc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
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return lowerToM1Enc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), emit.code);
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},
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0b01 => {
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// sal reg1, .cl
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// MC
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return lowerToMcEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
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return lowerToMcEnc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), emit.code);
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},
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0b10 => {
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// sal reg1, imm8
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// MI
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const imm = @truncate(u8, emit.mir.instructions.items(.data)[inst].imm);
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return lowerToMiImm8Enc(tag, RegisterOrMemory.reg(ops.reg1), imm, emit.code);
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return lowerToMiImm8Enc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), imm, emit.code);
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},
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0b11 => {
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return emit.fail("TODO unused variant: SHIFT reg1, 0b11", .{});
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@ -774,7 +796,7 @@ fn mirMulDiv(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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if (ops.reg1 != .none) {
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assert(ops.reg2 == .none);
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return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
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return lowerToMEnc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), emit.code);
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}
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assert(ops.reg1 == .none);
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assert(ops.reg2 != .none);
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@ -797,24 +819,35 @@ fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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return lowerToRmEnc(.imul, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
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return lowerToRmEnc(
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.imul,
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.{ .register = ops.reg1 },
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RegisterOrMemory.reg(.{ .register = ops.reg2 }),
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emit.code,
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);
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},
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0b01 => {
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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const src_reg: ?Register = if (ops.reg2 == .none) null else ops.reg2;
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return lowerToRmEnc(.imul, ops.reg1, RegisterOrMemory.mem(.qword_ptr, .{
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const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;
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return lowerToRmEnc(.imul, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.qword_ptr, .{
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.disp = imm,
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.base = src_reg,
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}), emit.code);
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},
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0b10 => {
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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return lowerToRmiEnc(.imul, ops.reg1, RegisterOrMemory.reg(ops.reg2), imm, emit.code);
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return lowerToRmiEnc(
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.imul,
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.{ .register = ops.reg1 },
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RegisterOrMemory.reg(.{ .register = ops.reg2 }),
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imm,
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emit.code,
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);
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},
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0b11 => {
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
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return lowerToRmiEnc(.imul, ops.reg1, RegisterOrMemory.mem(.qword_ptr, .{
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return lowerToRmiEnc(.imul, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.qword_ptr, .{
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.disp = imm_pair.dest_off,
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.base = ops.reg2,
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}), imm_pair.operand, emit.code);
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@ -842,10 +875,10 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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// lea reg1, [reg2 + imm32]
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// RM
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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const src_reg: ?Register = if (ops.reg2 == .none) null else ops.reg2;
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const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;
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return lowerToRmEnc(
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.lea,
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ops.reg1,
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.{ .register = ops.reg1 },
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RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
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.disp = imm,
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.base = src_reg,
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@ -859,7 +892,7 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const start_offset = emit.code.items.len;
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try lowerToRmEnc(
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.lea,
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ops.reg1,
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.{ .register = ops.reg1 },
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RegisterOrMemory.rip(Memory.PtrSize.fromBits(ops.reg1.size()), 0),
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emit.code,
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);
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@ -873,14 +906,14 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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0b10 => {
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// lea reg, [rbp + rcx + imm32]
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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const src_reg: ?Register = if (ops.reg2 == .none) null else ops.reg2;
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const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;
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const scale_index = ScaleIndex{
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.scale = 0,
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.index = .rcx,
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};
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return lowerToRmEnc(
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.lea,
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ops.reg1,
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.{ .register = ops.reg1 },
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RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
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.disp = imm,
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.base = src_reg,
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@ -903,7 +936,7 @@ fn mirLeaPie(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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// RM
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try lowerToRmEnc(
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.lea,
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ops.reg1,
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.{ .register = ops.reg1 },
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RegisterOrMemory.rip(Memory.PtrSize.fromBits(ops.reg1.size()), 0),
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emit.code,
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);
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@ -1489,11 +1522,11 @@ inline fn getModRmExt(tag: Tag) ?u3 {
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const ScaleIndex = struct {
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scale: u2,
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||||
index: Register,
|
||||
index: GpRegister,
|
||||
};
|
||||
|
||||
const Memory = struct {
|
||||
base: ?Register,
|
||||
base: ?GpRegister,
|
||||
rip: bool = false,
|
||||
disp: u32,
|
||||
ptr_size: PtrSize,
|
||||
@ -1595,6 +1628,40 @@ fn encodeImm(encoder: Encoder, imm: u32, size: u64) void {
|
||||
}
|
||||
}
|
||||
|
||||
const Register = union(enum) {
|
||||
register: GpRegister,
|
||||
avx_register: AvxRegister,
|
||||
|
||||
fn reg(register: GpRegister) Register {
|
||||
return .{ .register = register };
|
||||
}
|
||||
|
||||
fn avxReg(register: AvxRegister) Register {
|
||||
return .{ .avx_register = register };
|
||||
}
|
||||
|
||||
fn lowId(register: Register) u3 {
|
||||
return switch (register) {
|
||||
.register => |r| r.lowId(),
|
||||
.avx_register => |r| r.lowId(),
|
||||
};
|
||||
}
|
||||
|
||||
fn size(register: Register) u64 {
|
||||
return switch (register) {
|
||||
.register => |r| r.size(),
|
||||
.avx_register => |r| r.size(),
|
||||
};
|
||||
}
|
||||
|
||||
fn isExtended(register: Register) bool {
|
||||
return switch (register) {
|
||||
.register => |r| r.isExtended(),
|
||||
.avx_register => |r| r.isExtended(),
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
const RegisterOrMemory = union(enum) {
|
||||
register: Register,
|
||||
memory: Memory,
|
||||
@ -1605,7 +1672,7 @@ const RegisterOrMemory = union(enum) {
|
||||
|
||||
fn mem(ptr_size: Memory.PtrSize, args: struct {
|
||||
disp: u32,
|
||||
base: ?Register = null,
|
||||
base: ?GpRegister = null,
|
||||
scale_index: ?ScaleIndex = null,
|
||||
}) RegisterOrMemory {
|
||||
return .{
|
||||
|
||||
@ -151,6 +151,11 @@ pub const AvxRegister = enum(u6) {
|
||||
};
|
||||
}
|
||||
|
||||
/// Returns whether the register is *extended*.
|
||||
pub fn isExtended(self: Register) bool {
|
||||
return @enumToInt(self) & 0x08 != 0;
|
||||
}
|
||||
|
||||
/// This returns the 4-bit register ID.
|
||||
pub fn id(self: AvxRegister) u4 {
|
||||
return @truncate(u4, @enumToInt(self));
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user