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x64: load/store to/from AVX registers for f64
This commit is contained in:
Jakub Konka
parent
0835486249
commit
357561840d
File diff suppressed because it is too large
Load Diff
@ -68,6 +68,7 @@ pub fn lowerMir(emit: *Emit) InnerError!void {
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const inst = @intCast(u32, index);
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try emit.code_offset_mapping.putNoClobber(emit.bin_file.allocator, inst, emit.code.items.len);
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switch (tag) {
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// GPR instructions
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.adc => try emit.mirArith(.adc, inst),
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.add => try emit.mirArith(.add, inst),
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.sub => try emit.mirArith(.sub, inst),
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@ -182,6 +183,10 @@ pub fn lowerMir(emit: *Emit) InnerError!void {
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.interrupt => try emit.mirInterrupt(inst),
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.nop => try emit.mirNop(),
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// AVX instructions
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.mov_f64 => try emit.mirMovF64(inst),
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// Pseudo-instructions
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.call_extern => try emit.mirCallExtern(inst),
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.dbg_line => try emit.mirDbgLine(inst),
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@ -245,7 +250,7 @@ fn mirSyscall(emit: *Emit) InnerError!void {
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}
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fn mirPushPop(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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// PUSH/POP reg
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@ -274,7 +279,7 @@ fn mirPushPop(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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}
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fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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const data = emit.mir.extraData(Mir.RegsToPushOrPop, payload).data;
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const regs = data.regs;
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@ -297,7 +302,7 @@ fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.I
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}
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fn mirJmpCall(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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const target = emit.mir.instructions.items(.data)[inst].inst;
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@ -336,7 +341,7 @@ fn mirJmpCall(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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}
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fn mirCondJmp(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const target = emit.mir.instructions.items(.data)[inst].inst;
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const tag = switch (mir_tag) {
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.cond_jmp_greater_less => switch (ops.flags) {
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@ -368,7 +373,7 @@ fn mirCondJmp(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerErr
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}
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fn mirCondSetByte(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const tag = switch (mir_tag) {
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.cond_set_byte_greater_less => switch (ops.flags) {
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0b00 => Tag.setge,
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@ -398,7 +403,7 @@ fn mirCondSetByte(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) Inne
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}
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fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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if (ops.flags == 0b00) {
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return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);
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}
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@ -418,7 +423,7 @@ fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .@"test");
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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if (ops.reg2 == .none) {
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@ -447,7 +452,7 @@ fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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fn mirRet(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .ret);
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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// RETF imm16
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@ -471,7 +476,7 @@ fn mirRet(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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}
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fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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if (ops.reg2 == .none) {
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@ -513,7 +518,7 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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}
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fn mirArithMemImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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assert(ops.reg2 == .none);
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
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@ -554,7 +559,7 @@ inline fn immOpSize(u_imm: u32) u8 {
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}
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fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const scale = ops.flags;
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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// OP reg1, [reg2 + scale*rcx + imm32]
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@ -570,7 +575,7 @@ fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
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}
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fn mirArithScaleDst(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const scale = ops.flags;
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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const scale_index = ScaleIndex{
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@ -594,7 +599,7 @@ fn mirArithScaleDst(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
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}
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fn mirArithScaleImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const scale = ops.flags;
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
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@ -611,7 +616,7 @@ fn mirArithScaleImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
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}
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fn mirArithMemIndexImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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assert(ops.reg2 == .none);
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
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@ -636,7 +641,7 @@ fn mirArithMemIndexImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!v
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fn mirMovSignExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const mir_tag = emit.mir.instructions.items(.tag)[inst];
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assert(mir_tag == .mov_sign_extend);
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const imm = if (ops.flags != 0b00) emit.mir.instructions.items(.data)[inst].imm else undefined;
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switch (ops.flags) {
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0b00 => {
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@ -667,7 +672,7 @@ fn mirMovSignExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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fn mirMovZeroExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const mir_tag = emit.mir.instructions.items(.tag)[inst];
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assert(mir_tag == .mov_zero_extend);
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const imm = if (ops.flags != 0b00) emit.mir.instructions.items(.data)[inst].imm else undefined;
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switch (ops.flags) {
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0b00 => {
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@ -694,7 +699,7 @@ fn mirMovZeroExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .movabs);
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const imm: u64 = if (ops.reg1.size() == 64) blk: {
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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const imm = emit.mir.extraData(Mir.Imm64, payload).data;
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@ -718,7 +723,7 @@ fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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fn mirFisttp(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .fisttp);
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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// the selecting between operand sizes for this particular `fisttp` instruction
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// is done via opcode instead of the usual prefixes.
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@ -740,7 +745,7 @@ fn mirFisttp(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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fn mirFld(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .fld);
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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// the selecting between operand sizes for this particular `fisttp` instruction
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// is done via opcode instead of the usual prefixes.
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@ -757,8 +762,9 @@ fn mirFld(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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};
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return lowerToMEnc(opcode, .{ .memory = mem_or_reg }, emit.code);
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}
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fn mirShift(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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// sal reg1, 1
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@ -783,7 +789,7 @@ fn mirShift(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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}
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fn mirMulDiv(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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if (ops.reg1 != .none) {
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assert(ops.reg2 == .none);
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return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
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@ -806,7 +812,7 @@ fn mirMulDiv(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .imul_complex);
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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return lowerToRmEnc(.imul, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);
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@ -835,7 +841,7 @@ fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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}
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fn mirCwd(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const tag: Tag = switch (ops.flags) {
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0b00 => .cbw,
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0b01 => .cwd,
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@ -848,7 +854,7 @@ fn mirCwd(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .lea);
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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switch (ops.flags) {
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0b00 => {
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// lea reg1, [reg2 + imm32]
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@ -908,7 +914,7 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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fn mirLeaPie(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .lea_pie);
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);
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const load_reloc = emit.mir.instructions.items(.data)[inst].load_reloc;
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// lea reg1, [rip + reloc]
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@ -947,6 +953,36 @@ fn mirLeaPie(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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}
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}
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// AVX instructions
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fn mirMovF64(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .mov_f64);
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const ops = emit.mir.instructions.items(.ops)[inst];
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const flags = @truncate(u2, ops);
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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switch (flags) {
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0b00 => {
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const decoded = Mir.Ops(AvxRegister, GpRegister).decode(ops);
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return lowerToRmEnc(.vmovsd, Register.avxReg(decoded.reg1), RegisterOrMemory.mem(.qword_ptr, .{
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.disp = imm,
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.base = decoded.reg2,
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}), emit.code);
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},
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0b01 => {
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const decoded = Mir.Ops(GpRegister, AvxRegister).decode(ops);
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return lowerToMrEnc(.vmovsd, RegisterOrMemory.mem(.qword_ptr, .{
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.disp = imm,
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.base = decoded.reg1,
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}), Register.avxReg(decoded.reg2), emit.code);
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},
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else => return emit.fail("TODO unused variant 0b{b} for mov_f64", .{flags}),
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}
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}
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// Pseudo-instructions
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fn mirCallExtern(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .call_extern);
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@ -14,7 +14,8 @@ const assert = std.debug.assert;
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const bits = @import("bits.zig");
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const Air = @import("../../Air.zig");
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const CodeGen = @import("CodeGen.zig");
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const Register = bits.Register;
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const GpRegister = bits.Register;
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const AvxRegister = bits.AvxRegister;
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instructions: std.MultiArrayList(Inst).Slice,
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/// The meaning of this data is determined by `Inst.Tag` value.
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@ -349,6 +350,12 @@ pub const Inst = struct {
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/// Nop
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nop,
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/// AVX instructions
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/// ops flags: form:
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/// 0b00 reg1, qword ptr [reg2 + imm32]
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/// 0b10 qword ptr [reg1 + imm32], reg2
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mov_f64,
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/// Pseudo-instructions
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/// call extern function
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/// Notes:
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@ -450,30 +457,32 @@ pub const DbgLineColumn = struct {
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column: u32,
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};
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pub const Ops = struct {
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reg1: Register = .none,
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reg2: Register = .none,
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flags: u2 = 0b00,
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pub fn Ops(comptime Reg1: type, comptime Reg2: type) type {
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return struct {
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reg1: Reg1 = .none,
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reg2: Reg2 = .none,
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flags: u2 = 0b00,
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pub fn encode(self: Ops) u16 {
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var ops: u16 = 0;
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ops |= @intCast(u16, @enumToInt(self.reg1)) << 9;
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ops |= @intCast(u16, @enumToInt(self.reg2)) << 2;
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ops |= self.flags;
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return ops;
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}
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pub fn encode(self: @This()) u16 {
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var ops: u16 = 0;
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ops |= @intCast(u16, @enumToInt(self.reg1)) << 9;
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ops |= @intCast(u16, @enumToInt(self.reg2)) << 2;
|
||||
ops |= self.flags;
|
||||
return ops;
|
||||
}
|
||||
|
||||
pub fn decode(ops: u16) Ops {
|
||||
const reg1 = @intToEnum(Register, @truncate(u7, ops >> 9));
|
||||
const reg2 = @intToEnum(Register, @truncate(u7, ops >> 2));
|
||||
const flags = @truncate(u2, ops);
|
||||
return .{
|
||||
.reg1 = reg1,
|
||||
.reg2 = reg2,
|
||||
.flags = flags,
|
||||
};
|
||||
}
|
||||
};
|
||||
pub fn decode(ops: u16) @This() {
|
||||
const reg1 = @intToEnum(Reg1, @truncate(u7, ops >> 9));
|
||||
const reg2 = @intToEnum(Reg2, @truncate(u7, ops >> 2));
|
||||
const flags = @truncate(u2, ops);
|
||||
return .{
|
||||
.reg1 = reg1,
|
||||
.reg2 = reg2,
|
||||
.flags = flags,
|
||||
};
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
pub fn deinit(mir: *Mir, gpa: std.mem.Allocator) void {
|
||||
mir.instructions.deinit(gpa);
|
||||
|
||||
@ -3,6 +3,7 @@ const Type = @import("../../type.zig").Type;
|
||||
const Target = std.Target;
|
||||
const assert = std.debug.assert;
|
||||
const Register = @import("bits.zig").Register;
|
||||
const AvxRegister = @import("bits.zig").AvxRegister;
|
||||
|
||||
pub const Class = enum { integer, sse, sseup, x87, x87up, complex_x87, memory, none };
|
||||
|
||||
@ -381,3 +382,8 @@ pub const caller_preserved_regs = [_]Register{ .rax, .rcx, .rdx, .rsi, .rdi, .r8
|
||||
pub const allocatable_registers = callee_preserved_regs ++ caller_preserved_regs;
|
||||
pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };
|
||||
pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };
|
||||
|
||||
pub const avx_regs = [_]AvxRegister{
|
||||
.ymm0, .ymm1, .ymm2, .ymm3, .ymm4, .ymm5, .ymm6, .ymm7,
|
||||
.ymm8, .ymm9, .ymm10, .ymm11, .ymm12, .ymm13, .ymm14, .ymm15,
|
||||
};
|
||||
|
||||
@ -78,13 +78,13 @@ pub fn generateFunction(
|
||||
debug_output: DebugInfoOutput,
|
||||
) GenerateSymbolError!FnResult {
|
||||
switch (bin_file.options.target.cpu.arch) {
|
||||
.arm,
|
||||
.armeb,
|
||||
=> return @import("arch/arm/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
.aarch64,
|
||||
.aarch64_be,
|
||||
.aarch64_32,
|
||||
=> return @import("arch/aarch64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
// .arm,
|
||||
// .armeb,
|
||||
// => return @import("arch/arm/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
// .aarch64,
|
||||
// .aarch64_be,
|
||||
// .aarch64_32,
|
||||
// => return @import("arch/aarch64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.arc => return Function(.arc).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.avr => return Function(.avr).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.bpfel => return Function(.bpfel).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
@ -101,9 +101,9 @@ pub fn generateFunction(
|
||||
//.r600 => return Function(.r600).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.amdgcn => return Function(.amdgcn).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.riscv32 => return Function(.riscv32).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
.riscv64 => return @import("arch/riscv64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
// .riscv64 => return @import("arch/riscv64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.sparc => return Function(.sparc).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
.sparc64 => return @import("arch/sparc64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
// .sparc64 => return @import("arch/sparc64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.sparcel => return Function(.sparcel).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.s390x => return Function(.s390x).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.tce => return Function(.tce).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
@ -129,9 +129,9 @@ pub fn generateFunction(
|
||||
//.renderscript32 => return Function(.renderscript32).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.renderscript64 => return Function(.renderscript64).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.ve => return Function(.ve).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
.wasm32,
|
||||
.wasm64,
|
||||
=> return @import("arch/wasm/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
// .wasm32,
|
||||
// .wasm64,
|
||||
// => return @import("arch/wasm/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
else => @panic("Backend architectures that don't have good support yet are commented out, to improve compilation performance. If you are interested in one of these other backends feel free to uncomment them. Eventually these will be completed, but stage1 is slow and a memory hog."),
|
||||
}
|
||||
}
|
||||
|
||||
@ -23,10 +23,15 @@ pub const AllocateRegistersError = error{
|
||||
CodegenFail,
|
||||
};
|
||||
|
||||
pub fn SpillFn(comptime Function: type, comptime Register: type) type {
|
||||
return fn (*Function, Register, Air.Inst.Index) anyerror!void;
|
||||
}
|
||||
|
||||
pub fn RegisterManager(
|
||||
comptime Function: type,
|
||||
comptime Register: type,
|
||||
comptime tracked_registers: []const Register,
|
||||
comptime spill_fn: SpillFn(Function, Register),
|
||||
) type {
|
||||
// architectures which do not have a concept of registers should
|
||||
// refrain from using RegisterManager
|
||||
@ -47,6 +52,7 @@ pub fn RegisterManager(
|
||||
allocated_registers: FreeRegInt = 0,
|
||||
/// Tracks registers which are locked from being allocated
|
||||
locked_registers: FreeRegInt = 0,
|
||||
function: *Function,
|
||||
|
||||
const Self = @This();
|
||||
|
||||
@ -55,8 +61,8 @@ pub fn RegisterManager(
|
||||
const FreeRegInt = std.meta.Int(.unsigned, tracked_registers.len);
|
||||
const ShiftInt = math.Log2Int(FreeRegInt);
|
||||
|
||||
fn getFunction(self: *Self) *Function {
|
||||
return @fieldParentPtr(Function, "register_manager", self);
|
||||
fn spillInstruction(self: *Self, reg: Register, inst: Air.Inst.Index) AllocateRegistersError!void {
|
||||
return try spill_fn(self.function, reg, inst);
|
||||
}
|
||||
|
||||
fn getRegisterMask(reg: Register) ?FreeRegInt {
|
||||
@ -251,14 +257,14 @@ pub fn RegisterManager(
|
||||
self.markRegUsed(reg);
|
||||
} else {
|
||||
const spilled_inst = self.registers[index];
|
||||
try self.getFunction().spillInstruction(reg, spilled_inst);
|
||||
try self.spillInstruction(reg, spilled_inst);
|
||||
}
|
||||
self.registers[index] = inst;
|
||||
} else {
|
||||
// Don't track the register
|
||||
if (!self.isRegFree(reg)) {
|
||||
const spilled_inst = self.registers[index];
|
||||
try self.getFunction().spillInstruction(reg, spilled_inst);
|
||||
try self.spillInstruction(reg, spilled_inst);
|
||||
self.freeReg(reg);
|
||||
}
|
||||
}
|
||||
@ -293,7 +299,7 @@ pub fn RegisterManager(
|
||||
// stack allocation.
|
||||
const spilled_inst = self.registers[index];
|
||||
self.registers[index] = tracked_inst;
|
||||
try self.getFunction().spillInstruction(reg, spilled_inst);
|
||||
try self.spillInstruction(reg, spilled_inst);
|
||||
} else {
|
||||
self.getRegAssumeFree(reg, tracked_inst);
|
||||
}
|
||||
@ -302,7 +308,7 @@ pub fn RegisterManager(
|
||||
// Move the instruction that was previously there to a
|
||||
// stack allocation.
|
||||
const spilled_inst = self.registers[index];
|
||||
try self.getFunction().spillInstruction(reg, spilled_inst);
|
||||
try self.spillInstruction(reg, spilled_inst);
|
||||
self.freeReg(reg);
|
||||
}
|
||||
}
|
||||
|
||||
18
src/test.zig
18
src/test.zig
@ -34,18 +34,18 @@ test {
|
||||
var ctx = TestContext.init(std.testing.allocator, arena);
|
||||
defer ctx.deinit();
|
||||
|
||||
{
|
||||
const dir_path = try std.fs.path.join(arena, &.{
|
||||
std.fs.path.dirname(@src().file).?, "..", "test", "cases",
|
||||
});
|
||||
// {
|
||||
// const dir_path = try std.fs.path.join(arena, &.{
|
||||
// std.fs.path.dirname(@src().file).?, "..", "test", "cases",
|
||||
// });
|
||||
|
||||
var dir = try std.fs.cwd().openDir(dir_path, .{ .iterate = true });
|
||||
defer dir.close();
|
||||
// var dir = try std.fs.cwd().openDir(dir_path, .{ .iterate = true });
|
||||
// defer dir.close();
|
||||
|
||||
ctx.addTestCasesFromDir(dir);
|
||||
}
|
||||
// ctx.addTestCasesFromDir(dir);
|
||||
// }
|
||||
|
||||
try @import("test_cases").addCases(&ctx);
|
||||
// try @import("test_cases").addCases(&ctx);
|
||||
|
||||
try ctx.run();
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user