mirror of
https://github.com/ziglang/zig.git
synced 2026-02-21 16:54:52 +00:00
x64: check for floating-point intrinsics in codegen
This commit is contained in:
Jakub Konka
parent
283f40e4e9
commit
5cbfd5819e
@ -39,7 +39,7 @@ const RegisterLock = RegisterManager.RegisterLock;
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const Register = bits.Register;
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const gp = abi.RegisterClass.gp;
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const avx = abi.RegisterClass.avx;
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const sse = abi.RegisterClass.sse;
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const InnerError = error{
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OutOfMemory,
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@ -881,15 +881,18 @@ fn allocRegOrMem(self: *Self, inst: Air.Inst.Index, reg_ok: bool) !MCValue {
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switch (elem_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO allocRegOrMem for Vector type", .{}),
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.Float => {
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// TODO check if AVX available
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const ptr_bytes: u64 = 32;
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if (abi_size <= ptr_bytes) {
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if (self.register_manager.tryAllocReg(inst, .{
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.selector_mask = avx,
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})) |reg| {
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return MCValue{ .register = registerAlias(reg, abi_size) };
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if (self.intrinsicsAllowed(elem_ty)) {
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const ptr_bytes: u64 = 32;
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if (abi_size <= ptr_bytes) {
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if (self.register_manager.tryAllocReg(inst, .{
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.selector_mask = sse,
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})) |reg| {
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return MCValue{ .register = registerAlias(reg, abi_size) };
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}
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}
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}
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return self.fail("TODO allocRegOrMem for Float type without SSE/AVX support", .{});
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},
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else => {
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// Make sure the type can fit in a register before we try to allocate one.
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@ -969,8 +972,11 @@ pub fn spillRegisters(self: *Self, comptime count: comptime_int, registers: [cou
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/// allocated. A second call to `copyToTmpRegister` may return the same register.
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/// This can have a side effect of spilling instructions to the stack to free up a register.
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fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
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const mask = switch (ty.zigTypeTag()) {
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.Float => avx,
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const mask: RegisterManager.RegisterBitSet = switch (ty.zigTypeTag()) {
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.Float => blk: {
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if (self.intrinsicsAllowed(ty)) break :blk sse;
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return self.fail("TODO copy {} to register", .{ty.fmtDebug()});
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},
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else => gp,
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};
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const reg: Register = try self.register_manager.allocReg(null, .{
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@ -985,8 +991,11 @@ fn copyToTmpRegister(self: *Self, ty: Type, mcv: MCValue) !Register {
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/// This can have a side effect of spilling instructions to the stack to free up a register.
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/// WARNING make sure that the allocated register matches the returned MCValue from an instruction!
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fn copyToRegisterWithInstTracking(self: *Self, reg_owner: Air.Inst.Index, ty: Type, mcv: MCValue) !MCValue {
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const mask = switch (ty.zigTypeTag()) {
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.Float => avx,
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const mask: RegisterManager.RegisterBitSet = switch (ty.zigTypeTag()) {
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.Float => blk: {
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if (self.intrinsicsAllowed(ty)) break :blk sse;
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return self.fail("TODO copy {} to register", .{ty.fmtDebug()});
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},
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else => gp,
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};
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const reg: Register = try self.register_manager.allocReg(reg_owner, .{
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@ -3469,27 +3478,32 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
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},
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.register => |src_reg| switch (dst_ty.zigTypeTag()) {
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.Float => {
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const actual_tag: Mir.Inst.Tag = switch (dst_ty.tag()) {
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.f32 => switch (mir_tag) {
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.add => Mir.Inst.Tag.add_f32,
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.cmp => Mir.Inst.Tag.cmp_f32,
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else => return self.fail("TODO genBinOpMir for f32 register-register with MIR tag {}", .{mir_tag}),
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},
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.f64 => switch (mir_tag) {
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.add => Mir.Inst.Tag.add_f64,
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.cmp => Mir.Inst.Tag.cmp_f64,
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else => return self.fail("TODO genBinOpMir for f64 register-register with MIR tag {}", .{mir_tag}),
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},
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else => return self.fail("TODO genBinOpMir for float register-register and type {}", .{dst_ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = actual_tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = dst_reg.to128(),
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.reg2 = src_reg.to128(),
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}),
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.data = undefined,
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});
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if (self.intrinsicsAllowed(dst_ty)) {
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const actual_tag: Mir.Inst.Tag = switch (dst_ty.tag()) {
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.f32 => switch (mir_tag) {
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.add => Mir.Inst.Tag.add_f32_avx,
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.cmp => Mir.Inst.Tag.cmp_f32_avx,
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else => return self.fail("TODO genBinOpMir for f32 register-register with MIR tag {}", .{mir_tag}),
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},
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.f64 => switch (mir_tag) {
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.add => Mir.Inst.Tag.add_f64_avx,
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.cmp => Mir.Inst.Tag.cmp_f64_avx,
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else => return self.fail("TODO genBinOpMir for f64 register-register with MIR tag {}", .{mir_tag}),
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},
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else => return self.fail("TODO genBinOpMir for float register-register and type {}", .{dst_ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = actual_tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = dst_reg.to128(),
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.reg2 = src_reg.to128(),
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}),
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.data = undefined,
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});
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return;
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}
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return self.fail("TODO genBinOpMir for float register-register and no intrinsics", .{});
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},
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else => {
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_ = try self.addInst(.{
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@ -5326,24 +5340,29 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
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.register => |reg| {
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switch (ty.zigTypeTag()) {
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.Float => {
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const tag: Mir.Inst.Tag = switch (ty.tag()) {
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.f32 => .mov_f32,
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.f64 => .mov_f64,
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else => return self.fail("TODO genSetStackArg for register for type {}", .{ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = switch (ty.tag()) {
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.f32 => .esp,
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.f64 => .rsp,
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else => unreachable,
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},
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.reg2 = reg.to128(),
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.flags = 0b01,
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}),
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.data = .{ .imm = @bitCast(u32, -stack_offset) },
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});
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if (self.intrinsicsAllowed(ty)) {
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const tag: Mir.Inst.Tag = switch (ty.tag()) {
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.f32 => .mov_f32_avx,
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.f64 => .mov_f64_avx,
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else => return self.fail("TODO genSetStackArg for register for type {}", .{ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = switch (ty.tag()) {
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.f32 => .esp,
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.f64 => .rsp,
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else => unreachable,
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},
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.reg2 = reg.to128(),
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.flags = 0b01,
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}),
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.data = .{ .imm = @bitCast(u32, -stack_offset) },
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});
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return;
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}
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return self.fail("TODO genSetStackArg for register with no intrinsics", .{});
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},
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else => {
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_ = try self.addInst(.{
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@ -5505,24 +5524,29 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
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switch (ty.zigTypeTag()) {
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.Float => {
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const tag: Mir.Inst.Tag = switch (ty.tag()) {
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.f32 => .mov_f32,
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.f64 => .mov_f64,
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else => return self.fail("TODO genSetStack for register for type {}", .{ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = switch (ty.tag()) {
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.f32 => base_reg.to32(),
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.f64 => base_reg.to64(),
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else => unreachable,
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},
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.reg2 = reg.to128(),
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.flags = 0b01,
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}),
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.data = .{ .imm = @bitCast(u32, -stack_offset) },
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});
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if (self.intrinsicsAllowed(ty)) {
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const tag: Mir.Inst.Tag = switch (ty.tag()) {
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.f32 => .mov_f32_avx,
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.f64 => .mov_f64_avx,
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else => return self.fail("TODO genSetStack for register for type {}", .{ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = switch (ty.tag()) {
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.f32 => base_reg.to32(),
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.f64 => base_reg.to64(),
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else => unreachable,
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},
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.reg2 = reg.to128(),
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.flags = 0b01,
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}),
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.data = .{ .imm = @bitCast(u32, -stack_offset) },
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});
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return;
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}
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return self.fail("TODO genSetStack for register for type float with no intrinsics", .{});
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},
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else => {
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if (!math.isPowerOfTwo(abi_size)) {
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@ -6026,21 +6050,25 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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},
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},
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.Float => {
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const tag: Mir.Inst.Tag = switch (ty.tag()) {
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.f32 => .mov_f32,
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.f64 => .mov_f64,
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else => return self.fail("TODO genSetReg from register for {}", .{ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = reg.to128(),
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.reg2 = src_reg.to128(),
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.flags = 0b10,
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}),
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.data = undefined,
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});
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return;
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if (self.intrinsicsAllowed(ty)) {
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const tag: Mir.Inst.Tag = switch (ty.tag()) {
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.f32 => .mov_f32_avx,
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.f64 => .mov_f64_avx,
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else => return self.fail("TODO genSetReg from register for {}", .{ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = reg.to128(),
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.reg2 = src_reg.to128(),
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.flags = 0b10,
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}),
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.data = undefined,
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});
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return;
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}
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return self.fail("TODO genSetReg from register for float with no intrinsics", .{});
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},
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else => {},
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}
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@ -6073,24 +6101,29 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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const base_reg = try self.register_manager.allocReg(null, .{ .selector_mask = gp });
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try self.loadMemPtrIntoRegister(base_reg, Type.usize, mcv);
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const tag: Mir.Inst.Tag = switch (ty.tag()) {
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.f32 => .mov_f32,
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.f64 => .mov_f64,
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else => return self.fail("TODO genSetReg from memory for {}", .{ty.fmtDebug()}),
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};
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if (self.intrinsicsAllowed(ty)) {
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const tag: Mir.Inst.Tag = switch (ty.tag()) {
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.f32 => .mov_f32_avx,
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.f64 => .mov_f64_avx,
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else => return self.fail("TODO genSetReg from memory for {}", .{ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = reg.to128(),
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.reg2 = switch (ty.tag()) {
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.f32 => base_reg.to32(),
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.f64 => base_reg.to64(),
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else => unreachable,
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},
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}),
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.data = .{ .imm = 0 },
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});
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_ = try self.addInst(.{
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.tag = tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = reg.to128(),
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.reg2 = switch (ty.tag()) {
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.f32 => base_reg.to32(),
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.f64 => base_reg.to64(),
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else => unreachable,
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},
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}),
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.data = .{ .imm = 0 },
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});
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return;
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}
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return self.fail("TODO genSetReg from memory for float with no intrinsics", .{});
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},
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else => {
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if (x <= math.maxInt(i32)) {
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@ -6183,24 +6216,27 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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},
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},
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.Float => {
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const tag: Mir.Inst.Tag = switch (ty.tag()) {
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.f32 => .mov_f32,
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.f64 => .mov_f64,
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else => return self.fail("TODO genSetReg from stack offset for {}", .{ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = reg.to128(),
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.reg2 = switch (ty.tag()) {
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.f32 => .ebp,
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.f64 => .rbp,
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else => unreachable,
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},
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}),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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return;
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if (self.intrinsicsAllowed(ty)) {
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const tag: Mir.Inst.Tag = switch (ty.tag()) {
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.f32 => .mov_f32_avx,
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.f64 => .mov_f64_avx,
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else => return self.fail("TODO genSetReg from stack offset for {}", .{ty.fmtDebug()}),
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};
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_ = try self.addInst(.{
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.tag = tag,
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.ops = Mir.Inst.Ops.encode(.{
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.reg1 = reg.to128(),
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.reg2 = switch (ty.tag()) {
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.f32 => .ebp,
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.f64 => .rbp,
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else => unreachable,
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},
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}),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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return;
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}
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return self.fail("TODO genSetReg from stack offset for float with no intrinsics", .{});
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},
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else => {},
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}
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@ -6995,3 +7031,12 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {
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},
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}
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}
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fn intrinsicsAllowed(self: *Self, ty: Type) bool {
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return switch (ty.tag()) {
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.f32,
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.f64,
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=> Target.x86.featureSetHasAny(self.target.cpu.features, .{ .avx, .avx2 }),
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else => unreachable, // TODO finish this off
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};
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}
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@ -183,14 +183,14 @@ pub fn lowerMir(emit: *Emit) InnerError!void {
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.nop => try emit.mirNop(),
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// AVX instructions
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.mov_f64 => try emit.mirMovFloatAvx(.vmovsd, inst),
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.mov_f32 => try emit.mirMovFloatAvx(.vmovss, inst),
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.mov_f64_avx => try emit.mirMovFloatAvx(.vmovsd, inst),
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.mov_f32_avx => try emit.mirMovFloatAvx(.vmovss, inst),
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.add_f64 => try emit.mirAddFloatAvx(.vaddsd, inst),
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.add_f32 => try emit.mirAddFloatAvx(.vaddss, inst),
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.add_f64_avx => try emit.mirAddFloatAvx(.vaddsd, inst),
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.add_f32_avx => try emit.mirAddFloatAvx(.vaddss, inst),
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.cmp_f64 => try emit.mirCmpFloatAvx(.vucomisd, inst),
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.cmp_f32 => try emit.mirCmpFloatAvx(.vucomiss, inst),
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.cmp_f64_avx => try emit.mirCmpFloatAvx(.vucomisd, inst),
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.cmp_f32_avx => try emit.mirCmpFloatAvx(.vucomiss, inst),
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// Pseudo-instructions
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.call_extern => try emit.mirCallExtern(inst),
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@ -350,18 +350,18 @@ pub const Inst = struct {
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/// 0b00 reg1, qword ptr [reg2 + imm32]
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/// 0b01 qword ptr [reg1 + imm32], reg2
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/// 0b10 reg1, reg2
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mov_f64,
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mov_f32,
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mov_f64_avx,
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mov_f32_avx,
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/// ops flags: form:
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/// 0b00 reg1, reg1, reg2
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add_f64,
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add_f32,
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add_f64_avx,
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add_f32_avx,
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/// ops flags: form:
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///
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cmp_f64,
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cmp_f32,
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cmp_f64_avx,
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cmp_f32_avx,
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/// Pseudo-instructions
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/// call extern function
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@ -383,11 +383,11 @@ pub const caller_preserved_regs = [_]Register{ .rax, .rcx, .rdx, .rsi, .rdi, .r8
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pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };
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pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };
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const avx_regs = [_]Register{
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const sse_avx_regs = [_]Register{
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.ymm0, .ymm1, .ymm2, .ymm3, .ymm4, .ymm5, .ymm6, .ymm7,
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.ymm8, .ymm9, .ymm10, .ymm11, .ymm12, .ymm13, .ymm14, .ymm15,
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};
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const allocatable_registers = callee_preserved_regs ++ caller_preserved_regs ++ avx_regs;
|
||||
const allocatable_registers = callee_preserved_regs ++ caller_preserved_regs ++ sse_avx_regs;
|
||||
pub const RegisterManager = RegisterManagerFn(@import("CodeGen.zig"), Register, &allocatable_registers);
|
||||
|
||||
// Register classes
|
||||
@ -401,7 +401,7 @@ pub const RegisterClass = struct {
|
||||
}, true);
|
||||
break :blk set;
|
||||
};
|
||||
pub const avx: RegisterBitSet = blk: {
|
||||
pub const sse: RegisterBitSet = blk: {
|
||||
var set = RegisterBitSet.initEmpty();
|
||||
set.setRangeValue(.{
|
||||
.start = caller_preserved_regs.len + callee_preserved_regs.len,
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user