mirror/zig
1
0
Fork 0
mirror of https://github.com/ziglang/zig.git synced 2026-01-04 20:43:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

x64: re-enable incremental tests

Browse Source
This commit is contained in:
Jakub Konka 2022-05-18 17:58:05 +02:00
parent 6d32498c55
commit 080d138b9d
3 changed files with 31 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/arch/x86_64/bits.zig
View File

@ -696,8 +696,8 @@ test "Encoder helpers - general purpose registers" {
});
encoder.opcode_2byte(0x0f, 0xaf);
encoder.modRm_direct(
Register.eax.lowId(),
Register.edi.lowId(),
Register.eax.lowEnc(),
Register.edi.lowEnc(),
);
try testing.expectEqualSlices(u8, &[_]u8{ 0x0f, 0xaf, 0xc7 }, code.items);
@ -716,8 +716,8 @@ test "Encoder helpers - general purpose registers" {
});
encoder.opcode_1byte(0x89);
encoder.modRm_direct(
Register.edi.lowId(),
Register.eax.lowId(),
Register.edi.lowEnc(),
Register.eax.lowEnc(),
);
try testing.expectEqualSlices(u8, &[_]u8{ 0x89, 0xf8 }, code.items);
@ -743,7 +743,7 @@ test "Encoder helpers - general purpose registers" {
encoder.opcode_1byte(0x81);
encoder.modRm_direct(
0,
Register.rcx.lowId(),
Register.rcx.lowEnc(),
);
encoder.imm32(2147483647);
@ -768,7 +768,7 @@ test "Encoder helpers - Vex prefix" {
{
stream.reset();
var vex_prefix = Encoder.Vex{};
vex_prefix.reg(Register.xmm15.id());
vex_prefix.reg(Register.xmm15.enc());
const nwritten = vex_prefix.write(writer);
try testing.expectEqualSlices(u8, &[_]u8{ 0xc5, 0x80 }, buf[0..nwritten]);
}
@ -808,7 +808,7 @@ test "Encoder helpers - Vex prefix" {
vex.simd_prefix_66();
encoder.vex(vex); // use 64 bit operation
encoder.opcode_1byte(0x28);
encoder.modRm_direct(0, Register.xmm1.lowId());
encoder.modRm_direct(0, Register.xmm1.lowEnc());
try testing.expectEqualSlices(u8, &[_]u8{ 0xC5, 0xF9, 0x28, 0xC1 }, code.items);
}
@ -822,10 +822,10 @@ test "Encoder helpers - Vex prefix" {
vex.simd_prefix_66();
vex.lead_opc_0f();
vex.rex(.{ .r = true });
vex.reg(Register.xmm1.id());
vex.reg(Register.xmm1.enc());
encoder.vex(vex);
encoder.opcode_1byte(0x16);
encoder.modRm_RIPDisp32(Register.xmm13.lowId());
encoder.modRm_RIPDisp32(Register.xmm13.lowEnc());
encoder.disp32(0);
try testing.expectEqualSlices(u8, &[_]u8{ 0xC5, 0x71, 0x16, 0x2D, 0x00, 0x00, 0x00, 0x00 }, code.items);
}

26
src/register_manager.zig
View File

@ -430,9 +430,9 @@ test "tryAllocReg: no spilling" {
const mock_instruction: Air.Inst.Index = 1;
try expectEqual(@as(?MockRegister1, .r2), function.register_manager.tryAllocReg(mock_instruction));
try expectEqual(@as(?MockRegister1, .r3), function.register_manager.tryAllocReg(mock_instruction));
try expectEqual(@as(?MockRegister1, null), function.register_manager.tryAllocReg(mock_instruction));
try expectEqual(@as(?MockRegister1, .r2), function.register_manager.tryAllocReg(mock_instruction, .{}));
try expectEqual(@as(?MockRegister1, .r3), function.register_manager.tryAllocReg(mock_instruction, .{}));
try expectEqual(@as(?MockRegister1, null), function.register_manager.tryAllocReg(mock_instruction, .{}));
try expect(function.register_manager.isRegAllocated(.r2));
try expect(function.register_manager.isRegAllocated(.r3));
@ -458,16 +458,16 @@ test "allocReg: spilling" {
const mock_instruction: Air.Inst.Index = 1;
try expectEqual(@as(?MockRegister1, .r2), try function.register_manager.allocReg(mock_instruction));
try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction));
try expectEqual(@as(?MockRegister1, .r2), try function.register_manager.allocReg(mock_instruction, .{}));
try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction, .{}));
// Spill a register
try expectEqual(@as(?MockRegister1, .r2), try function.register_manager.allocReg(mock_instruction));
try expectEqual(@as(?MockRegister1, .r2), try function.register_manager.allocReg(mock_instruction, .{}));
try expectEqualSlices(MockRegister1, &[_]MockRegister1{.r2}, function.spilled.items);
// No spilling necessary
function.register_manager.freeReg(.r3);
try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction));
try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction, .{}));
try expectEqualSlices(MockRegister1, &[_]MockRegister1{.r2}, function.spilled.items);
// Locked registers
@ -476,7 +476,7 @@ test "allocReg: spilling" {
const lock = function.register_manager.lockReg(.r2);
defer if (lock) |reg| function.register_manager.unlockReg(reg);
try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction));
try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction, .{}));
}
try expect(!function.register_manager.lockedRegsExist());
}
@ -489,7 +489,7 @@ test "tryAllocRegs" {
};
defer function.deinit();
try expectEqual([_]MockRegister2{ .r0, .r1, .r2 }, function.register_manager.tryAllocRegs(3, .{ null, null, null }).?);
try expectEqual([_]MockRegister2{ .r0, .r1, .r2 }, function.register_manager.tryAllocRegs(3, .{ null, null, null }, .{}).?);
try expect(function.register_manager.isRegAllocated(.r0));
try expect(function.register_manager.isRegAllocated(.r1));
@ -504,7 +504,7 @@ test "tryAllocRegs" {
const lock = function.register_manager.lockReg(.r1);
defer if (lock) |reg| function.register_manager.unlockReg(reg);
try expectEqual([_]MockRegister2{ .r0, .r2, .r3 }, function.register_manager.tryAllocRegs(3, .{ null, null, null }).?);
try expectEqual([_]MockRegister2{ .r0, .r2, .r3 }, function.register_manager.tryAllocRegs(3, .{ null, null, null }, .{}).?);
}
try expect(!function.register_manager.lockedRegsExist());
@ -543,7 +543,7 @@ test "allocRegs: normal usage" {
const lock = function.register_manager.lockReg(result_reg);
defer if (lock) |reg| function.register_manager.unlockReg(reg);
const regs = try function.register_manager.allocRegs(2, .{ null, null });
const regs = try function.register_manager.allocRegs(2, .{ null, null }, .{});
try function.genAdd(result_reg, regs[0], regs[1]);
}
}
@ -565,12 +565,12 @@ test "allocRegs: selectively reducing register pressure" {
// Here, we don't defer unlock because we manually unlock
// after genAdd
const regs = try function.register_manager.allocRegs(2, .{ null, null });
const regs = try function.register_manager.allocRegs(2, .{ null, null }, .{});
try function.genAdd(result_reg, regs[0], regs[1]);
function.register_manager.unlockReg(lock.?);
const extra_summand_reg = try function.register_manager.allocReg(null);
const extra_summand_reg = try function.register_manager.allocReg(null, .{});
try function.genAdd(result_reg, result_reg, extra_summand_reg);
}
}

18
src/test.zig
View File

@ -34,18 +34,18 @@ test {
var ctx = TestContext.init(std.testing.allocator, arena);
defer ctx.deinit();
// {
// const dir_path = try std.fs.path.join(arena, &.{
// std.fs.path.dirname(@src().file).?, "..", "test", "cases",
// });
{
const dir_path = try std.fs.path.join(arena, &.{
std.fs.path.dirname(@src().file).?, "..", "test", "cases",
});
// var dir = try std.fs.cwd().openDir(dir_path, .{ .iterate = true });
// defer dir.close();
var dir = try std.fs.cwd().openDir(dir_path, .{ .iterate = true });
defer dir.close();
// ctx.addTestCasesFromDir(dir);
// }
ctx.addTestCasesFromDir(dir);
}
// try @import("test_cases").addCases(&ctx);
try @import("test_cases").addCases(&ctx);
try ctx.run();
}