13017 Commits

Author SHA1 Message Date
Andrew Kelley
68f4eb0f67 stage2: fully implement Type.eql for pointers
Also fixed abiAlignment - for pointers it was returning the abi
alignment inside the type, rather than of the pointer itself. There is
now `ptrAlignment` for getting the alignment inside the type of
pointers.
2021-03-27 23:55:19 -07:00
Andrew Kelley
95cc457d97 stage2: enable passing tests 2021-03-26 23:54:36 -07:00
Andrew Kelley
1f5617ac07 stage2: implement bitwise expr and error literals 2021-03-26 23:46:37 -07:00
Andrew Kelley
da731e18c9 stage2: implement source location: .node_offset_var_decl_ty 2021-03-26 18:35:15 -07:00
Andrew Kelley
a72bfd00cf astgen: fix continue expressions 2021-03-26 18:26:39 -07:00
Isaac Freund
a217ad59c7
astgen: fix result location for sliced objects 2021-03-26 23:39:29 +01:00
Isaac Freund
22338d7816
astgen: implement float literals 2021-03-26 15:46:50 +01:00
Isaac Freund
d8ee8794e1
astgen: implement more builtin functions 2021-03-26 15:20:11 +01:00
Isaac Freund
5eea13f5cc
astgen: implement slicing 2021-03-26 11:46:42 +01:00
Andrew Kelley
b2deaf8027 stage2: improve source locations of Decl access
* zir.Code: introduce a decls array. This is so that `decl_val` and
   `decl_ref` instructions can refer to a Decl with a u32 and therefore
   they can also store a source location. This is needed for proper
   compile error reporting.
 * astgen uses a hash map to avoid redundantly adding a Decl to the
   decls array.
 * fixed reporting "instruction illegal outside function body" instead
   of the desired message "unable to resolve comptime value".
 * astgen skips emitting dbg_stmt instructions in comptime scopes.
 * astgen has some logic to avoid adding unnecessary type coercion
   instructions for common values.
2021-03-25 23:45:17 -07:00
Andrew Kelley
4bfcd105ef stage2: fix @compileLog. 2021-03-25 20:11:23 -07:00
Andrew Kelley
4fd3a2e8e8 astgen: fix var decl source locations 2021-03-25 19:39:30 -07:00
Andrew Kelley
b9c5a1fdf5 astgen: fix for loop expressions
also rename the ZIR instruction `deref_node` to `load`.
2021-03-25 19:25:26 -07:00
Andrew Kelley
399bb2e154 astgen: fix array access 2021-03-25 13:03:54 -07:00
Andrew Kelley
31023de6c4 stage2: implement inline while
Introduce "inline" variants of ZIR tags:
 * block => block_inline
 * repeat => repeat_inline
 * break => break_inline
 * condbr => condbr_inline

The inline variants perform control flow at compile-time, and they
utilize the return value of `Sema.analyzeBody`.

`analyzeBody` now returns an Index, not a Ref, which is the ZIR index of
a break instruction. This effectively communicates both the intended
break target block as well as the operand, allowing parent blocks to
find out whether they, in turn, should return the break instruction up the
call stack, or accept the operand as the block's result and continue
analyzing instructions in the block.

Additionally:
 * removed the deprecated ZIR tag `block_comptime`.
 * removed `break_void_node` so that all break instructions use the same Data.
 * zir.Code: remove the `root_start` and `root_len` fields. There is now
   implied to be a block at index 0 for the root body. This is so that
   `break_inline` has something to point at and we no longer need the
   special instruction `break_flat`.
 * implement source location byteOffset() for .node_offset_if_cond
   .node_offset_for_cond is probably redundant and can be deleted.

We don't have `comptime var` supported yet, so this commit adds a test
that at least makes sure the condition is required to be comptime known
for `inline while`.
2021-03-25 00:55:36 -07:00
Andrew Kelley
12d18a36e5 stage2: enable passing tests 2021-03-24 20:58:38 -07:00
Andrew Kelley
01bfd835bb stage2: clean up break / noreturn astgen
* Module.addBreak and addBreakVoid return zir.Inst.Index not Ref
   because Index is the simpler type and we never need a Ref for these.
 * astgen: make noreturn stuff return the unreachable_value and avoid
   unnecessary calls to rvalue()
 * breakExpr: avoid unnecessary access into the tokens array
 * breakExpr: fix incorrect `@intCast` (previously this unsafely
   casted an Index to a Ref)
2021-03-24 20:45:14 -07:00
Timon Kruiper
ea42ab34ab stage2: add block test cases llvm backend 2021-03-24 19:54:03 -07:00
Timon Kruiper
522707622e astgen: implement breaking from a block 2021-03-24 19:54:03 -07:00
Andrew Kelley
d73a4940e0 stage2: cleanups from previous commits
Change some ZIR instructions from un_tok to un_node. Idea here is to
avoid needlessly accessing the tokens array.

Go ahead and finish the catch code in orelseCatchExpr. Otherwise it
would be an easy mistake to get the scopes wrong when updating that
code and introduce a bug.

Delete a function that is now dead code.
2021-03-24 16:14:11 -07:00
Timon Kruiper
3543373fd4 stage2: add passing optional test case in LLVM backend 2021-03-24 15:48:18 -07:00
Timon Kruiper
2c99fbb672 astgen: implement orelse 2021-03-24 15:48:18 -07:00
Andrew Kelley
0c6581e01d stage2: fix memory leak when updating a function 2021-03-24 15:46:06 -07:00
Andrew Kelley
180dae4196 stage2: further cleanups regarding zir.Inst.Ref
* Introduce helper functions on Module.WipZirCode and zir.Code
 * Move some logic around
 * re-introduce ref_start_index
 * prefer usize for local variables + `@intCast` at the end.
   Empirically this is easier to optimize.
 * Avoid using mem.{bytesAsSlice,sliceAsBytes} because it incurs an
   unnecessary multiplication/division which may cause problems for the
   optimizer.
 * Use a regular enum, not packed, for `Ref`. Memory layout is
   guaranteed for enums which specify their tag type. Packed enums have
   ABI alignment of 1 byte which is too small.
2021-03-24 15:36:23 -07:00
Isaac Freund
0c601965ab
stage2: make zir.Inst.Ref a non-exhaustive enum
This provides us greatly increased type safety and prevents the common
mistake of using a zir.Inst.Ref where a zir.Inst.Index was expected or
vice-versa. It also increases the ergonomics of using the typed values
which can be directly referenced with a Ref over the previous zir.Const
approach.

The main pain point is casting between a []Ref and []u32, which could be
alleviated in the future with a new std.mem function.
2021-03-24 19:11:44 +01:00
Andrew Kelley
a1afe69395 stage2: comment out failing test cases; implement more things
* comment out the failing stage2 test cases
   (so that we can uncomment the ones that are newly passing with
   further commits)
 * Sema: implement negate, negatewrap
 * astgen: implement field access, multiline string literals, and
   character literals
 * Module: when resolving an AST node into a byte offset, use the
   main_tokens array, not the firstToken function
2021-03-23 23:13:01 -07:00
Andrew Kelley
13ced07f23 stage2: fix while loops
also start to form a plan for how inline while loops will work
2021-03-23 21:37:10 -07:00
Andrew Kelley
bf7c3e9355 astgen: fixups regarding var decls and rl_ptr 2021-03-23 16:47:41 -07:00
Andrew Kelley
be673e6793 stage2: implement inttype ZIR
also add i128 and u128 to const inst list
2021-03-23 16:12:26 -07:00
Andrew Kelley
aa46a705ad astgen: finishThenElseBlock: fix putting store_to_block_ptr in wrong block 2021-03-23 15:32:25 -07:00
Andrew Kelley
af73f79490 stage2: fix comptimeExpr and comptime function calls 2021-03-23 13:25:58 -07:00
Andrew Kelley
866be099f8 stage2: add helper functions to clean up astgen Ref/Index 2021-03-23 12:54:18 -07:00
Timon Kruiper
830143905e Sema: use correct LazySrcLoc for resolvePeerTypes 2021-03-23 11:56:06 -07:00
Timon Kruiper
7194baed66 astgen: implement typeof 2021-03-23 11:56:06 -07:00
Timon Kruiper
99cf9f8bf1 astgen: fix an issue where the alloc wasnt elided 2021-03-23 11:49:12 -07:00
Timon Kruiper
982df37135 stage2: handle void value in genRet in LLVM backend 2021-03-23 11:42:46 -07:00
Timon Kruiper
d73b0473a1 stage2: rename fail to todo in LLVM backend
This way we don't have to pass src to every function and we can simply
use the first node as the lazy source location for all the todo
errors.
2021-03-23 11:42:46 -07:00
Isaac Freund
668148549a
stage2: fix two return types to be Ref not Index
We currently have no type safety between zir.Inst.Ref, zir.Inst.Index,
and plain u32s.
2021-03-23 11:58:43 +01:00
Timon Kruiper
f3e8073e05 astgen: implement assign operations 2021-03-23 11:40:55 +01:00
Andrew Kelley
d24be85be8 stage2: fix if expressions 2021-03-22 23:47:13 -07:00
Andrew Kelley
568f333681 astgen: improve the ensure_unused_result elision 2021-03-22 18:57:46 -07:00
Andrew Kelley
2f391df2a7 stage2: Sema improvements and boolean logic astgen
* add `Module.setBlockBody` and related functions
 * redo astgen for `and` and `or` to use fewer ZIR instructions and
   require less processing for comptime known values
 * Sema: rework `analyzeBody` function. See the new doc comments in this
   commit. Divides ZIR instructions up into 3 categories:
   - always noreturn
   - never noreturn
   - sometimes noreturn
2021-03-22 17:29:56 -07:00
Isaac Freund
9f0b9b8da1
stage2: remove all async related code
The current plan is to avoid using async and related features in the
stage2 compiler so that we can bootstrap before implementing them.

Having this untested and incomplete code in the codebase increases
friction while working on stage2, in particular when preforming
larger refactors such as the current zir memory layout rework.

Therefore remove all async related code, leaving only error messages
in astgen.
2021-03-23 00:23:41 +01:00
Dimenus
240b15381d fix calculation in ensureCapacity 2021-03-22 11:58:44 -07:00
Isaac Freund
f3770dcc30
astgen: implement pointer types 2021-03-22 16:03:00 +01:00
Isaac Freund
8111453cc1
astgen: implement array types 2021-03-22 14:54:13 +01:00
Andrew Kelley
4f3071a817 cleanups from previous commit 2021-03-21 20:18:13 -07:00
jacob gw
7a55671b89 zir-memory-layout: astgen: varDecl 2021-03-21 20:10:27 -07:00
Andrew Kelley
5769c963e0 Sema: implement arithmetic 2021-03-21 19:23:12 -07:00
Andrew Kelley
07c204393f Sema: no explicit coercion needed for inline asm args
These are now done with result locations.
2021-03-21 17:55:31 -07:00