mirror/zig
1
0
Fork 0
mirror of https://github.com/ziglang/zig.git synced 2025-12-24 07:03:11 +00:00
Code Issues Packages Projects Releases Wiki Activity

astgen: fix array access

Browse Source
This commit is contained in:
Andrew Kelley 2021-03-25 13:03:54 -07:00
parent 31023de6c4
commit 399bb2e154
3 changed files with 36 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
BRANCH_TODO
View File

@ -20,6 +20,7 @@ Merge TODO list:
Performance optimizations to look into:
* astgen: pass *GenZir as the first arg, not *Module
- point here is to avoid the unnecessary virtual call scope.getGenZir()
* don't store end index for blocks; rely on last instruction being noreturn
* look into not storing the field name of field access as a string in zir
instructions. or, look into introducing interning to string_bytes (local

28
src/astgen.zig
View File

@ -1838,25 +1838,21 @@ fn arrayAccess(
rl: ResultLoc,
node: ast.Node.Index,
) InnerError!zir.Inst.Ref {
if (true) @panic("TODO update for zir-memory-layout");
const tree = scope.tree();
const gz = scope.getGenZir();
const tree = gz.tree();
const main_tokens = tree.nodes.items(.main_token);
const node_datas = tree.nodes.items(.data);
const usize_type = try addZIRInstConst(mod, scope, src, .{
.ty = Type.initTag(.type),
.val = Value.initTag(.usize_type),
});
const index_rl: ResultLoc = .{ .ty = usize_type };
switch (rl) {
.ref => return addZirInstTag(mod, scope, src, .elem_ptr, .{
.array = try expr(mod, scope, .ref, node_datas[node].lhs),
.index = try expr(mod, scope, index_rl, node_datas[node].rhs),
}),
else => return rvalue(mod, scope, rl, try addZirInstTag(mod, scope, src, .elem_val, .{
.array = try expr(mod, scope, .none, node_datas[node].lhs),
.index = try expr(mod, scope, index_rl, node_datas[node].rhs),
})),
.ref => return gz.addBin(
.elem_ptr,
try expr(mod, scope, .ref, node_datas[node].lhs),
try expr(mod, scope, .{ .ty = .usize_type }, node_datas[node].rhs),
),
else => return rvalue(mod, scope, rl, try gz.addBin(
.elem_val,
try expr(mod, scope, .none, node_datas[node].lhs),
try expr(mod, scope, .{ .ty = .usize_type }, node_datas[node].rhs),
), node),
}
}

46
test/stage2/test.zig
View File

@ -917,29 +917,29 @@ pub fn addCases(ctx: *TestContext) !void {
);
// Array access.
//case.addCompareOutput(
// \\export fn _start() noreturn {
// \\ assert("hello"[0] == 'h');
// \\
// \\ exit();
// \\}
// \\
// \\pub fn assert(ok: bool) void {
// \\ if (!ok) unreachable; // assertion failure
// \\}
// \\
// \\fn exit() noreturn {
// \\ asm volatile ("syscall"
// \\ :
// \\ : [number] "{rax}" (231),
// \\ [arg1] "{rdi}" (0)
// \\ : "rcx", "r11", "memory"
// \\ );
// \\ unreachable;
// \\}
//,
// "",
//);
case.addCompareOutput(
\\export fn _start() noreturn {
\\ assert("hello"[0] == 'h');
\\
\\ exit();
\\}
\\
\\pub fn assert(ok: bool) void {
\\ if (!ok) unreachable; // assertion failure
\\}
\\
\\fn exit() noreturn {
\\ asm volatile ("syscall"
\\ :
\\ : [number] "{rax}" (231),
\\ [arg1] "{rdi}" (0)
\\ : "rcx", "r11", "memory"
\\ );
\\ unreachable;
\\}
,
"",
);
// 64bit set stack
case.addCompareOutput(