50 Commits

Author SHA1 Message Date
Jacob Young
dbe1b4a7e5 x86_64: fix value tracking bugs 2023-03-24 17:57:58 -04:00
Jacob Young
f316cb29cc x86_64: implement atomic and fence ops 2023-03-21 08:49:54 +01:00
Jakub Konka
c746cbc686 codegen: move gen logic for typed values, consts and decl ref to common codegen 2023-03-03 18:06:25 +01:00
Andrew Kelley
aeaef8c0ff update std lib and compiler sources to new for loop syntax 2023-02-18 19:17:21 -07:00
InKryption
a0d3a87ce1 std.fmt: require specifier for unwrapping ?T and E!T 2022-07-26 11:25:49 -07:00
Andrew Kelley
934573fc5d Revert "std.fmt: require specifier for unwrapping ?T and E!T."
This reverts commit 7cbd586ace46a8e8cebab660ebca3cfc049305d9.

This is causing a fail to build from source:

```
./lib/std/fmt.zig:492:17: error: cannot format optional without a specifier (i.e. {?} or {any})
                @compileError("cannot format optional without a specifier (i.e. {?} or {any})");
                ^
./src/link/MachO/Atom.zig:544:26: note: called from here
                log.debug("  RELA({s}) @ {x} => %{d} in object({d})", .{
                         ^
```

I looked at the code to fix it but none of those args are optionals.
2022-07-24 11:50:10 -07:00
InKryption
7cbd586ace
std.fmt: require specifier for unwrapping ?T and E!T.
Co-authored-by: Veikka Tuominen <git@vexu.eu>
2022-07-24 12:01:56 +03:00
Jakub Konka
117f9f69e7 x64: simplify saving registers to stack in prologue 2022-06-07 19:33:40 +02:00
Jakub Konka
0e0b00fd48 regalloc: use StaticBitSet internally 2022-05-26 12:05:51 +02:00
Jakub Konka
800edb03b5 regalloc: test allocating from multiple register claases 2022-05-21 08:40:47 +02:00
Jakub Konka
0e43d007c0 regalloc: temporarily nerf back to raw ints until stage2 catches up 2022-05-20 07:36:15 +02:00
Jakub Konka
e95dfac03e regalloc: make register class bitmask non-optional 2022-05-19 23:54:48 +02:00
Jakub Konka
283f40e4e9 x64: use StaticBitSet instead of an integer internally in RegisterManager 2022-05-19 19:39:34 +02:00
Jakub Konka
080d138b9d x64: re-enable incremental tests 2022-05-19 19:39:34 +02:00
Jakub Konka
f346150820 x64: use register classes mask to select between gp and avx 2022-05-19 19:39:34 +02:00
Jakub Konka
549174f743 regalloc: allow for optional selector mask when allocating 2022-05-19 19:39:32 +02:00
Jakub Konka
9e5c8cb008 x64: merge general purpose with simd register into one bitset
This way, we do not have to tweak the `RegisterManager` to handle
multiple register types - we have one linear space instead. Additionally
we can use the bitset itself to separate the registers into overlapping
(the ones that are aliases of differing bitwidths) and nonoverlapping
classes (for example, AVX registers do not overlap general purpose
registers, thus they can be allocated simultaneously).

Another huge benefit of this simple approach is the fact that we can
still refer to *all* registers regardless of their class via enum
literals which makes the code so much more readable.

Finally, `RegisterLock` is universal across different register classes.
2022-05-19 19:37:29 +02:00
Jakub Konka
2aee230251 x64: add unordered cmp with EFLAGS 2022-05-19 19:37:28 +02:00
Jakub Konka
357561840d x64: load/store to/from AVX registers for f64 2022-05-19 19:36:35 +02:00
Jakub Konka
f57b059e58 regalloc: refactor locking multiple registers at once 2022-05-07 13:27:11 +02:00
Jakub Konka
bf11cdc9d8 x64: refactor code to avoid stage1 sema limitations 2022-05-07 13:19:53 +02:00
Jakub Konka
197c2a465f regalloc: rename freeze/unfreeze to lock/unlock registers 2022-05-07 10:46:05 +02:00
Jakub Konka
43a627927f x64: fix misused register locks 2022-05-07 10:31:08 +02:00
Jakub Konka
ac954eb539 regalloc: ensure we only freeze/unfreeze at the outermost scope
This prevents a nasty type of bugs where we accidentally unfreeze
a register that was frozen purposely in the outer scope, risking
accidental realloc of a taken register.

Fix CF flags spilling on aarch64 backend.
2022-05-07 00:57:55 +02:00
joachimschmidt557
13321c8070 stage2 regalloc: fix tryAllocRegs for specific situations
Previously, tryAllocRegs did not take frozen registers into account
when checking if enough registers are available.
2022-03-18 19:37:01 +01:00
joachimschmidt557
4590e980f7
stage2 ARM: implement caller-saved registers 2022-03-11 14:12:11 +01:00
joachimschmidt557
06058ed6f3
stage2 regalloc: replace Register.allocIndex with generic indexOfReg
* callee_preserved_regs and other ABI-specific information have been
moved to the respective abi.zig files
2022-03-11 13:29:16 +01:00
joachimschmidt557
f5068107cd stage2 regalloc: track Inst instead of ?Inst in register mapping
The information whether a register is allocated to an instruction is
already encoded in the free_registers "bitmap". Duplicating that
information in the registers map is unnecessary and may lead to
performance degradations.
2022-02-13 23:24:26 +01:00
joachimschmidt557
4b3b487627 stage2 regalloc: Introduce error.OutOfRegisters 2022-02-06 00:14:48 +01:00
Jakub Konka
74a01e3d64 stage2: remove the concept of register exceptions 2022-02-03 18:08:29 +01:00
joachimschmidt557
1a324a8ad6 stage2 regalloc: Fix bug where regs were not marked as allocated 2022-01-28 18:03:03 -05:00
joachimschmidt557
35503b3d3f stage2 regalloc: Add freezeRegs/unfreezeRegs API
The freeze/unfreeze API replaces the exceptions API for hopefully
preventing bugs in codegen code using the RegisterManager. The
exceptions API is still available for backwards compatibility and will
be removed once all backends transition to the new freeze/unfreeze
API.
2022-01-26 18:23:27 +01:00
joachimschmidt557
69d03d3a29
stage2 ARM: implement struct_field_ptr and struct_field_val 2021-12-30 14:39:06 +01:00
Lee Cannon
85de022c56
allocgate: std Allocator interface refactor 2021-11-30 23:32:47 +00:00
Lewis Gaul
7381431e68 Get register_manager.zig tests to compile - use value '1' as mock Air.Inst.Index 2021-07-20 12:19:16 -07:00
Andrew Kelley
913393fd3b stage2: first pass over Module.zig for AIR memory layout 2021-07-20 12:19:16 -07:00
Andrew Kelley
ee6432537e stage2: first pass over codegen.zig for AIR memory layout 2021-07-20 12:19:16 -07:00
Andrew Kelley
5d6f7b44c1 stage2: rework AIR memory layout
This commit changes the AIR file and the documentation of the memory
layout. The actual work of modifying the surrounding code (in Sema and
codegen) is not yet done.
2021-07-20 12:18:14 -07:00
Jacob G-W
9fffffb07b fix code broken from previous commit 2021-06-21 17:03:03 -07:00
Jacob G-W
641ecc260f std, src, doc, test: remove unused variables 2021-06-21 17:03:03 -07:00
Andrew Kelley
79dee75b1c stage2: rename ir.zig to air.zig
We've settled on the nomenclature for the artifacts the compiler
pipeline produces:

1. Tokens
2. AST (Abstract Syntax Tree)
3. ZIR (Zig Intermediate Representation)
4. AIR (Analyzed Intermediate Representation)
5. Machine Code

Renaming `ir` identifiers to `air` will come with the inevitable
air-memory-layout branch that I plan to start after the 0.8.0 release.
2021-05-22 14:29:16 -07:00
joachimschmidt557
8b4e91e18c stage2 register manager: clean up API and add more unit tests 2021-05-14 15:12:33 -04:00
joachimschmidt557
d211dc37c8 stage2 ARM: Overhaul of genArmBinOp 2021-05-09 08:48:58 +02:00
Veikka Tuominen
42a95197f3 update usage of std.testing in stage2 2021-05-08 15:15:30 +03:00
joachimschmidt557
3a55cda14d stage2 register manager: Use an array instead of a hashmap for tracking
allocated registers
2021-04-25 13:20:53 -04:00
joachimschmidt557
5edabb3990 stage2 register manager: Add functions for allocating multiple registers 2021-04-16 13:03:10 -04:00
joachimschmidt557
4ff5a3cd94
stage2 regalloc: Add unit test for getReg 2021-04-07 15:15:14 +02:00
joachimschmidt557
ac2211118f
stage2 regalloc: Add getReg and getRegWithoutTracking 2021-04-06 21:14:00 +02:00
joachimschmidt557
228a1ce3e8 stage2 register_manager: Add unit tests for tryAllocReg and allocReg 2021-04-02 12:01:52 -07:00
joachimschmidt557
4efbcad26d stage2 codegen: Extract register management code into separate file 2021-04-02 12:01:52 -07:00