x86_64: fix value tracking bugs

This commit is contained in:
Jacob Young 2023-03-23 00:27:25 -04:00
parent f99b75360d
commit dbe1b4a7e5
8 changed files with 182 additions and 143 deletions

View File

@ -265,12 +265,15 @@ pub fn generate(
const fn_type = fn_owner_decl.ty;
var branch_stack = std.ArrayList(Branch).init(bin_file.allocator);
try branch_stack.ensureUnusedCapacity(2);
// The outermost branch is used for constants only.
branch_stack.appendAssumeCapacity(.{});
branch_stack.appendAssumeCapacity(.{});
defer {
assert(branch_stack.items.len == 1);
branch_stack.items[0].deinit(bin_file.allocator);
assert(branch_stack.items.len == 2);
for (branch_stack.items) |*branch| branch.deinit(bin_file.allocator);
branch_stack.deinit();
}
try branch_stack.append(.{});
var function = Self{
.gpa = bin_file.allocator,
@ -1070,20 +1073,29 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
if (self.air_bookkeeping < old_air_bookkeeping + 1) {
std.debug.panic("in codegen.zig, handling of AIR instruction %{d} ('{}') did not do proper bookkeeping. Look for a missing call to finishAir.", .{ inst, air_tags[inst] });
}
{ // check consistency of tracked registers
var it = self.register_manager.free_registers.iterator(.{ .kind = .unset });
while (it.next()) |index| {
const tracked_inst = self.register_manager.registers[index];
switch (air_tags[tracked_inst]) {
.block => {},
else => assert(RegisterManager.indexOfRegIntoTracked(
switch (self.getResolvedInstValue(tracked_inst).?) {
.register => |reg| reg,
.register_overflow => |ro| ro.reg,
else => unreachable,
},
).? == index),
}
}
}
}
}
}
/// Asserts there is already capacity to insert into top branch inst_table.
fn processDeath(self: *Self, inst: Air.Inst.Index) void {
const air_tags = self.air.instructions.items(.tag);
if (air_tags[inst] == .constant) return; // Constants are immortal.
const prev_value = self.getResolvedInstValue(inst) orelse return;
log.debug("%{d} => {}", .{ inst, MCValue.dead });
// When editing this function, note that the logic must synchronize with `reuseOperand`.
const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
branch.inst_table.putAssumeCapacity(inst, .dead);
switch (prev_value) {
fn freeValue(self: *Self, value: MCValue) void {
switch (value) {
.register => |reg| {
self.register_manager.freeReg(reg);
},
@ -1098,6 +1110,18 @@ fn processDeath(self: *Self, inst: Air.Inst.Index) void {
}
}
/// Asserts there is already capacity to insert into top branch inst_table.
fn processDeath(self: *Self, inst: Air.Inst.Index) void {
const air_tags = self.air.instructions.items(.tag);
if (air_tags[inst] == .constant) return; // Constants are immortal.
const prev_value = self.getResolvedInstValue(inst) orelse return;
log.debug("%{d} => {}", .{ inst, MCValue.dead });
// When editing this function, note that the logic must synchronize with `reuseOperand`.
const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
branch.inst_table.putAssumeCapacity(inst, .dead);
self.freeValue(prev_value);
}
/// Called when there are no operands, and the instruction is always unreferenced.
fn finishAirBookkeeping(self: *Self) void {
if (std.debug.runtime_safety) {
@ -1140,13 +1164,17 @@ fn finishAir(self: *Self, inst: Air.Inst.Index, result: MCValue, operands: [Live
},
else => {},
}
} else switch (result) {
.none, .dead, .unreach => {},
else => unreachable, // Why didn't the result die?
}
self.finishAirBookkeeping();
}
fn ensureProcessDeathCapacity(self: *Self, additional_count: usize) !void {
// In addition to the caller's needs, we need enough space to spill every register and eflags.
const table = &self.branch_stack.items[self.branch_stack.items.len - 1].inst_table;
try table.ensureUnusedCapacity(self.gpa, additional_count);
try table.ensureUnusedCapacity(self.gpa, additional_count + self.register_manager.registers.len + 1);
}
fn allocMem(self: *Self, inst: ?Air.Inst.Index, abi_size: u32, abi_align: u32) !u32 {
@ -1252,12 +1280,15 @@ fn captureState(self: *Self) !State {
};
}
fn revertState(self: *Self, state: State) void {
fn revertState(self: *Self, state: State) !void {
var stack = try state.stack.clone(self.gpa);
errdefer stack.deinit(self.gpa);
self.register_manager.registers = state.registers;
self.eflags_inst = state.eflags_inst;
self.stack.deinit(self.gpa);
self.stack = state.stack;
self.stack = stack;
self.next_stack_offset = state.next_stack_offset;
self.register_manager.free_registers = state.free_registers;
@ -1277,7 +1308,7 @@ pub fn spillInstruction(self: *Self, reg: Register, inst: Air.Inst.Index) !void
else => {},
}
const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
try branch.inst_table.put(self.gpa, inst, stack_mcv);
branch.inst_table.putAssumeCapacity(inst, stack_mcv);
try self.genSetStack(self.air.typeOfIndex(inst), stack_mcv.stack_offset, reg_mcv, .{});
}
@ -1294,7 +1325,7 @@ pub fn spillEflagsIfOccupied(self: *Self) !void {
log.debug("spilling %{d} to mcv {any}", .{ inst_to_save, new_mcv });
const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
try branch.inst_table.put(self.gpa, inst_to_save, new_mcv);
branch.inst_table.putAssumeCapacity(inst_to_save, new_mcv);
self.eflags_inst = null;
@ -1347,13 +1378,23 @@ fn copyToRegisterWithInstTracking(self: *Self, reg_owner: Air.Inst.Index, ty: Ty
}
fn airAlloc(self: *Self, inst: Air.Inst.Index) !void {
const stack_offset = try self.allocMemPtr(inst);
return self.finishAir(inst, .{ .ptr_stack_offset = @intCast(i32, stack_offset) }, .{ .none, .none, .none });
const result: MCValue = result: {
if (self.liveness.isUnused(inst)) break :result .dead;
const stack_offset = try self.allocMemPtr(inst);
break :result .{ .ptr_stack_offset = @intCast(i32, stack_offset) };
};
return self.finishAir(inst, result, .{ .none, .none, .none });
}
fn airRetPtr(self: *Self, inst: Air.Inst.Index) !void {
const stack_offset = try self.allocMemPtr(inst);
return self.finishAir(inst, .{ .ptr_stack_offset = @intCast(i32, stack_offset) }, .{ .none, .none, .none });
const result: MCValue = result: {
if (self.liveness.isUnused(inst)) break :result .dead;
const stack_offset = try self.allocMemPtr(inst);
break :result .{ .ptr_stack_offset = @intCast(i32, stack_offset) };
};
return self.finishAir(inst, result, .{ .none, .none, .none });
}
fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {
@ -1992,11 +2033,6 @@ fn airUnwrapErrUnionErr(self: *Self, inst: Air.Inst.Index) !void {
},
.register => |reg| {
// TODO reuse operand
self.register_manager.getRegAssumeFree(.rcx, null);
const rcx_lock =
if (err_off > 0) self.register_manager.lockRegAssumeUnused(.rcx) else null;
defer if (rcx_lock) |lock| self.register_manager.unlockReg(lock);
const eu_lock = self.register_manager.lockReg(reg);
defer if (eu_lock) |lock| self.register_manager.unlockReg(lock);
@ -2047,11 +2083,6 @@ fn genUnwrapErrorUnionPayloadMir(
},
.register => |reg| {
// TODO reuse operand
self.register_manager.getRegAssumeFree(.rcx, null);
const rcx_lock =
if (payload_off > 0) self.register_manager.lockRegAssumeUnused(.rcx) else null;
defer if (rcx_lock) |lock| self.register_manager.unlockReg(lock);
const eu_lock = self.register_manager.lockReg(reg);
defer if (eu_lock) |lock| self.register_manager.unlockReg(lock);
@ -2877,17 +2908,18 @@ fn airPopcount(self: *Self, inst: Air.Inst.Index) !void {
const imm_0000_1111 = Immediate.u(mask / 0b0001_0001);
const imm_0000_0001 = Immediate.u(mask / 0b1111_1111);
const tmp_reg = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
src_mcv.register
const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
src_mcv
else
try self.copyToTmpRegister(src_ty, src_mcv);
const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
defer self.register_manager.unlockReg(tmp_lock);
const dst_reg = try self.register_manager.allocReg(inst, gp);
try self.copyToRegisterWithInstTracking(inst, src_ty, src_mcv);
const dst_reg = dst_mcv.register;
const dst_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
defer self.register_manager.unlockReg(dst_lock);
const tmp_reg = try self.register_manager.allocReg(null, gp);
const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
defer self.register_manager.unlockReg(tmp_lock);
{
const dst = registerAlias(dst_reg, src_abi_size);
const tmp = registerAlias(tmp_reg, src_abi_size);
@ -2896,9 +2928,9 @@ fn airPopcount(self: *Self, inst: Air.Inst.Index) !void {
else
undefined;
// tmp = operand
try self.asmRegisterRegister(.mov, dst, tmp);
// dst = operand
try self.asmRegisterRegister(.mov, tmp, dst);
// tmp = operand
try self.asmRegisterImmediate(.shr, tmp, Immediate.u(1));
// tmp = operand >> 1
if (src_abi_size > 4) {
@ -2948,7 +2980,7 @@ fn airPopcount(self: *Self, inst: Air.Inst.Index) !void {
}
// dst = (temp3 * 0x01...01) >> (bits - 8)
}
break :result .{ .register = dst_reg };
break :result dst_mcv;
};
return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
}
@ -3796,8 +3828,6 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValue
/// Clobbers .rcx for non-immediate shift value.
fn genShiftBinOpMir(self: *Self, tag: Mir.Inst.Tag, ty: Type, reg: Register, shift: MCValue) !void {
assert(reg.to64() != .rcx);
switch (tag) {
.sal, .sar, .shl, .shr => {},
else => unreachable,
@ -4612,23 +4642,24 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
const src_index = self.air.instructions.items(.data)[inst].arg.src_index;
const name = self.mod_fn.getParamName(self.bin_file.options.module.?, src_index);
if (self.liveness.isUnused(inst))
return self.finishAirBookkeeping();
const result: MCValue = result: {
if (self.liveness.isUnused(inst)) break :result .dead;
const dst_mcv: MCValue = switch (mcv) {
.register => |reg| blk: {
self.register_manager.getRegAssumeFree(reg.to64(), inst);
break :blk MCValue{ .register = reg };
},
.stack_offset => |off| blk: {
const offset = @intCast(i32, self.max_end_stack) - off + 16;
break :blk MCValue{ .stack_offset = -offset };
},
else => return self.fail("TODO implement arg for {}", .{mcv}),
const dst_mcv: MCValue = switch (mcv) {
.register => |reg| blk: {
self.register_manager.getRegAssumeFree(reg.to64(), inst);
break :blk MCValue{ .register = reg };
},
.stack_offset => |off| blk: {
const offset = @intCast(i32, self.max_end_stack) - off + 16;
break :blk MCValue{ .stack_offset = -offset };
},
else => return self.fail("TODO implement arg for {}", .{mcv}),
};
try self.genArgDbgInfo(ty, name, dst_mcv);
break :result dst_mcv;
};
try self.genArgDbgInfo(ty, name, dst_mcv);
return self.finishAir(inst, dst_mcv, .{ .none, .none, .none });
return self.finishAir(inst, result, .{ .none, .none, .none });
}
fn genArgDbgInfo(self: Self, ty: Type, name: [:0]const u8, mcv: MCValue) !void {
@ -4924,6 +4955,8 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallModifier
}
const result: MCValue = result: {
if (self.liveness.isUnused(inst)) break :result .dead;
switch (info.return_value) {
.register => {
// Save function return value in a new register
@ -5137,7 +5170,10 @@ fn genTry(
const reloc = try self.genCondBrMir(Type.anyerror, is_err_mcv);
try self.genBody(body);
try self.performReloc(reloc);
const result = try self.genUnwrapErrorUnionPayloadMir(inst, err_union_ty, err_union);
const result = if (self.liveness.isUnused(inst))
.dead
else
try self.genUnwrapErrorUnionPayloadMir(inst, err_union_ty, err_union);
return result;
}
@ -5234,7 +5270,8 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
}
// Capture the state of register and stack allocation state so that we can revert to it.
const saved_state = try self.captureState();
var saved_state = try self.captureState();
defer saved_state.deinit(self.gpa);
{
try self.branch_stack.append(.{});
@ -5252,7 +5289,7 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
var then_branch = self.branch_stack.pop();
defer then_branch.deinit(self.gpa);
self.revertState(saved_state);
try self.revertState(saved_state);
try self.performReloc(reloc);
@ -5286,9 +5323,7 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
log.debug("Then branch: {}", .{then_branch.fmtDebug()});
log.debug("Else branch: {}", .{else_branch.fmtDebug()});
const parent_branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
try self.canonicaliseBranches(parent_branch, &then_branch, &else_branch);
try self.canonicaliseBranches(true, &then_branch, &else_branch);
// We already took care of pl_op.operand earlier, so we're going
// to pass .none here
@ -5423,10 +5458,6 @@ fn isErr(self: *Self, maybe_inst: ?Air.Inst.Index, ty: Type, operand: MCValue) !
try self.genBinOpMir(.cmp, Type.anyerror, .{ .stack_offset = offset }, .{ .immediate = 0 });
},
.register => |reg| {
self.register_manager.getRegAssumeFree(.rcx, null);
const rcx_lock = if (err_off > 0) self.register_manager.lockRegAssumeUnused(.rcx) else null;
defer if (rcx_lock) |lock| self.register_manager.unlockReg(lock);
const eu_lock = self.register_manager.lockReg(reg);
defer if (eu_lock) |lock| self.register_manager.unlockReg(lock);
@ -5606,7 +5637,7 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {
// break instruction will choose a MCValue for the block result and overwrite
// this field. Following break instructions will use that MCValue to put their
// block results.
.mcv = .none,
.mcv = if (self.liveness.isUnused(inst)) .dead else .none,
});
defer self.blocks.getPtr(inst).?.relocs.deinit(self.gpa);
@ -5646,21 +5677,29 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
}
}
var branch_stack = std.ArrayList(Branch).init(self.gpa);
defer {
for (branch_stack.items) |*bs| {
bs.deinit(self.gpa);
}
branch_stack.deinit();
log.debug("airSwitch: %{d}", .{inst});
log.debug("Upper branches:", .{});
for (self.branch_stack.items) |bs| {
log.debug("{}", .{bs.fmtDebug()});
}
try branch_stack.ensureTotalCapacityPrecise(switch_br.data.cases_len + 1);
var prev_branch: ?Branch = null;
defer if (prev_branch) |*branch| branch.deinit(self.gpa);
// Capture the state of register and stack allocation state so that we can revert to it.
var saved_state = try self.captureState();
defer saved_state.deinit(self.gpa);
const cases_len = switch_br.data.cases_len + @boolToInt(switch_br.data.else_body_len > 0);
while (case_i < switch_br.data.cases_len) : (case_i += 1) {
const case = self.air.extraData(Air.SwitchBr.Case, extra_index);
const items = @ptrCast([]const Air.Inst.Ref, self.air.extra[case.end..][0..case.data.items_len]);
const case_body = self.air.extra[case.end + items.len ..][0..case.data.body_len];
extra_index = case.end + items.len + case_body.len;
// Revert to the previous register and stack allocation state.
if (prev_branch) |_| try self.revertState(saved_state);
var relocs = try self.gpa.alloc(u32, items.len);
defer self.gpa.free(relocs);
@ -5671,12 +5710,9 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
reloc.* = try self.asmJccReloc(undefined, .ne);
}
// Capture the state of register and stack allocation state so that we can revert to it.
const saved_state = try self.captureState();
{
try self.branch_stack.append(.{});
errdefer _ = self.branch_stack.pop();
if (cases_len > 1) try self.branch_stack.append(.{});
errdefer _ = if (cases_len > 1) self.branch_stack.pop();
try self.ensureProcessDeathCapacity(liveness.deaths[case_i].len);
for (liveness.deaths[case_i]) |operand| {
@ -5686,25 +5722,31 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
try self.genBody(case_body);
}
branch_stack.appendAssumeCapacity(self.branch_stack.pop());
// Consolidate returned MCValues between prongs like we do in airCondBr.
if (cases_len > 1) {
var case_branch = self.branch_stack.pop();
errdefer case_branch.deinit(self.gpa);
// Revert to the previous register and stack allocation state.
self.revertState(saved_state);
for (relocs) |reloc| {
try self.performReloc(reloc);
log.debug("Case-{d} branch: {}", .{ case_i, case_branch.fmtDebug() });
if (prev_branch) |*canon_branch| {
try self.canonicaliseBranches(case_i == cases_len - 1, canon_branch, &case_branch);
canon_branch.deinit(self.gpa);
}
prev_branch = case_branch;
}
for (relocs) |reloc| try self.performReloc(reloc);
}
if (switch_br.data.else_body_len > 0) {
const else_body = self.air.extra[extra_index..][0..switch_br.data.else_body_len];
// Capture the state of register and stack allocation state so that we can revert to it.
const saved_state = try self.captureState();
// Revert to the previous register and stack allocation state.
if (prev_branch) |_| try self.revertState(saved_state);
{
try self.branch_stack.append(.{});
errdefer _ = self.branch_stack.pop();
if (cases_len > 1) try self.branch_stack.append(.{});
errdefer _ = if (cases_len > 1) self.branch_stack.pop();
const else_deaths = liveness.deaths.len - 1;
try self.ensureProcessDeathCapacity(liveness.deaths[else_deaths].len);
@ -5715,53 +5757,48 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
try self.genBody(else_body);
}
branch_stack.appendAssumeCapacity(self.branch_stack.pop());
// Consolidate returned MCValues between a prong and the else branch like we do in airCondBr.
if (cases_len > 1) {
var else_branch = self.branch_stack.pop();
errdefer else_branch.deinit(self.gpa);
// Revert to the previous register and stack allocation state.
self.revertState(saved_state);
log.debug("Else branch: {}", .{else_branch.fmtDebug()});
if (prev_branch) |*canon_branch| {
try self.canonicaliseBranches(true, canon_branch, &else_branch);
canon_branch.deinit(self.gpa);
}
prev_branch = else_branch;
}
}
// Consolidate returned MCValues between prongs and else branch like we do
// in airCondBr.
log.debug("airSwitch: %{d}", .{inst});
log.debug("Upper branches:", .{});
for (self.branch_stack.items) |bs| {
log.debug("{}", .{bs.fmtDebug()});
}
for (branch_stack.items, 0..) |bs, i| {
log.debug("Case-{d} branch: {}", .{ i, bs.fmtDebug() });
}
// TODO: can we reduce the complexity of this algorithm?
const parent_branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
var i: usize = branch_stack.items.len;
while (i > 1) : (i -= 1) {
const canon_branch = &branch_stack.items[i - 2];
const target_branch = &branch_stack.items[i - 1];
try self.canonicaliseBranches(parent_branch, canon_branch, target_branch);
}
// We already took care of pl_op.operand earlier, so we're going
// to pass .none here
// We already took care of pl_op.operand earlier, so we're going to pass .none here
return self.finishAir(inst, .unreach, .{ .none, .none, .none });
}
fn canonicaliseBranches(self: *Self, parent_branch: *Branch, canon_branch: *Branch, target_branch: *Branch) !void {
try parent_branch.inst_table.ensureUnusedCapacity(self.gpa, target_branch.inst_table.count());
fn canonicaliseBranches(
self: *Self,
update_parent: bool,
canon_branch: *Branch,
target_branch: *const Branch,
) !void {
const parent_branch =
if (update_parent) &self.branch_stack.items[self.branch_stack.items.len - 1] else undefined;
if (update_parent) try self.ensureProcessDeathCapacity(target_branch.inst_table.count());
const target_slice = target_branch.inst_table.entries.slice();
for (target_slice.items(.key), target_slice.items(.value)) |target_key, target_value| {
const canon_mcv = if (canon_branch.inst_table.fetchSwapRemove(target_key)) |canon_entry| blk: {
// The instruction's MCValue is overridden in both branches.
parent_branch.inst_table.putAssumeCapacity(target_key, canon_entry.value);
if (update_parent) {
parent_branch.inst_table.putAssumeCapacity(target_key, canon_entry.value);
}
if (target_value == .dead) {
assert(canon_entry.value == .dead);
continue;
}
break :blk canon_entry.value;
} else blk: {
if (target_value == .dead)
continue;
if (target_value == .dead) continue;
// The instruction is only overridden in the else branch.
// If integer overflows occurs, the question is: why wasn't the instruction marked dead?
break :blk self.getResolvedInstValue(target_key).?;
@ -5770,22 +5807,25 @@ fn canonicaliseBranches(self: *Self, parent_branch: *Branch, canon_branch: *Bran
// TODO make sure the destination stack offset / register does not already have something
// going on there.
try self.setRegOrMem(self.air.typeOfIndex(target_key), canon_mcv, target_value);
self.freeValue(target_value);
// TODO track the new register / stack allocation
}
try parent_branch.inst_table.ensureUnusedCapacity(self.gpa, canon_branch.inst_table.count());
if (update_parent) try self.ensureProcessDeathCapacity(canon_branch.inst_table.count());
const canon_slice = canon_branch.inst_table.entries.slice();
for (canon_slice.items(.key), canon_slice.items(.value)) |canon_key, canon_value| {
// We already deleted the items from this table that matched the target_branch.
// So these are all instructions that are only overridden in the canon branch.
parent_branch.inst_table.putAssumeCapacity(canon_key, canon_value);
log.debug("canon_value = {}", .{canon_value});
if (canon_value == .dead)
continue;
const parent_mcv = self.getResolvedInstValue(canon_key).?;
const parent_mcv =
if (canon_value != .dead) self.getResolvedInstValue(canon_key).? else undefined;
if (update_parent) {
parent_branch.inst_table.putAssumeCapacity(canon_key, canon_value);
}
if (canon_value == .dead) continue;
log.debug("consolidating canon_entry {d} {}=>{}", .{ canon_key, parent_mcv, canon_value });
// TODO make sure the destination stack offset / register does not already have something
// going on there.
try self.setRegOrMem(self.air.typeOfIndex(canon_key), parent_mcv, canon_value);
try self.setRegOrMem(self.air.typeOfIndex(canon_key), canon_value, parent_mcv);
self.freeValue(parent_mcv);
// TODO track the new register / stack allocation
}
}
@ -5811,11 +5851,9 @@ fn airBr(self: *Self, inst: Air.Inst.Index) !void {
fn br(self: *Self, block: Air.Inst.Index, operand: Air.Inst.Ref) !void {
const block_data = self.blocks.getPtr(block).?;
if (self.air.typeOf(operand).hasRuntimeBits()) {
if (block_data.mcv != .dead and self.air.typeOf(operand).hasRuntimeBits()) {
const operand_mcv = try self.resolveInst(operand);
const block_mcv = block_data.mcv;
if (block_mcv == .none) {
if (block_data.mcv == .none) {
block_data.mcv = switch (operand_mcv) {
.none, .dead, .unreach => unreachable,
.register, .stack_offset, .memory => operand_mcv,
@ -5827,7 +5865,7 @@ fn br(self: *Self, block: Air.Inst.Index, operand: Air.Inst.Ref) !void {
else => return self.fail("TODO implement block_data.mcv = operand_mcv for {}", .{operand_mcv}),
};
} else {
try self.setRegOrMem(self.air.typeOfIndex(block), block_mcv, operand_mcv);
try self.setRegOrMem(self.air.typeOfIndex(block), block_data.mcv, operand_mcv);
}
}
return self.brVoid(block);
@ -6916,7 +6954,8 @@ fn airAtomicRmw(self: *Self, inst: Air.Inst.Index) !void {
const pl_op = self.air.instructions.items(.data)[inst].pl_op;
const extra = self.air.extraData(Air.AtomicRmw, pl_op.payload).data;
const dst_reg = try self.register_manager.allocReg(inst, gp);
const unused = self.liveness.isUnused(inst);
const dst_reg = try self.register_manager.allocReg(if (unused) null else inst, gp);
const ptr_ty = self.air.typeOf(pl_op.operand);
const ptr_mcv = try self.resolveInst(pl_op.operand);
@ -6924,7 +6963,6 @@ fn airAtomicRmw(self: *Self, inst: Air.Inst.Index) !void {
const val_ty = self.air.typeOf(extra.operand);
const val_mcv = try self.resolveInst(extra.operand);
const unused = self.liveness.isUnused(inst);
try self.atomicOp(dst_reg, ptr_mcv, val_mcv, ptr_ty, val_ty, unused, extra.op(), extra.ordering());
const result: MCValue = if (unused) .dead else .{ .register = dst_reg };
return self.finishAir(inst, result, .{ pl_op.operand, extra.operand, .none });

View File

@ -523,7 +523,7 @@ pub fn getCAbiIntReturnRegs(target: Target) []const Register {
}
const gp_regs = [_]Register{
.rbx, .r12, .r13, .r14, .r15, .rax, .rcx, .rdx, .rsi, .rdi, .r8, .r9, .r10, .r11,
.rax, .rcx, .rdx, .rbx, .rsi, .rdi, .r8, .r9, .r10, .r11, .r12, .r13, .r14, .r15,
};
const sse_avx_regs = [_]Register{
.ymm0, .ymm1, .ymm2, .ymm3, .ymm4, .ymm5, .ymm6, .ymm7,

View File

@ -210,13 +210,14 @@ pub fn RegisterManager(
}
assert(i == count);
for (regs, 0..) |reg, j| {
for (regs, insts) |reg, inst| {
log.debug("tryAllocReg {} for inst {?}", .{ reg, inst });
self.markRegAllocated(reg);
if (insts[j]) |inst| {
if (inst) |tracked_inst| {
// Track the register
const index = indexOfRegIntoTracked(reg).?; // indexOfReg() on a callee-preserved reg should never return null
self.registers[index] = inst;
self.registers[index] = tracked_inst;
self.markRegUsed(reg);
}
}
@ -258,6 +259,7 @@ pub fn RegisterManager(
if (excludeRegister(reg, register_class)) break;
if (self.isRegLocked(reg)) continue;
log.debug("allocReg {} for inst {?}", .{ reg, insts[i] });
regs[i] = reg;
self.markRegAllocated(reg);
const index = indexOfRegIntoTracked(reg).?; // indexOfReg() on a callee-preserved reg should never return null

View File

@ -191,6 +191,7 @@ test "nested arrays of strings" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
const array_of_strings = [_][]const u8{ "hello", "this", "is", "my", "thing" };
for (array_of_strings, 0..) |s, i| {

View File

@ -6,7 +6,6 @@ fn retOpt() ?u32 {
test "breaking from a loop in an if statement" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
var cond = true;

View File

@ -275,6 +275,7 @@ test "two counters" {
test "1-based counter and ptr to array" {
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
var ok: usize = 0;

View File

@ -112,7 +112,6 @@ test "if prongs cast to expected type instead of peer type resolution" {
}
test "if peer expressions inferred optional type" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO

View File

@ -1514,7 +1514,6 @@ test "packed union with zero-bit field" {
}
test "reinterpreting enum value inside packed union" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO