18758 Commits

Author SHA1 Message Date
Veikka Tuominen
15ec55406d std: fix ambiguous references 2022-06-06 13:11:50 -07:00
Veikka Tuominen
84000aa820 Sema: fix inline call of func using ret_ptr with comptime only type 2022-06-06 13:11:50 -07:00
Veikka Tuominen
8fa88c88c2 AstGen: fix coercion scope type when stores are eliminated 2022-06-06 13:11:50 -07:00
Veikka Tuominen
cb5d2b691a Sema: validate equality on store to comptime field 2022-06-06 13:11:50 -07:00
Veikka Tuominen
a040ccb42f Sema: fix coerce result ptr outside of functions 2022-06-06 13:11:50 -07:00
joachimschmidt557
8ca6dc33d1
stage2 AArch64: implement try AIR instruction 2022-06-06 21:27:36 +02:00
Andrew Kelley
41bf81dc32 Revert "Treat blocks with "return" as "noreturn""
This reverts commit 135b91aecd9be1f6f5806b667e07e383dd481198.

"endsWithBreak()" is not a meaningful question to ask and should not be
used this way. A simple example that defeats this logic is:

```zig
export fn entry() void {
    outer: {
        {
            break :outer;
        }
        return;
    }
}
```
2022-06-06 11:31:54 -07:00
Jakub Konka
e05de31a5f dwarf: fix incorrect type reloc for unions
Split type relocs into two kinds: local and global. Global relocs
use a global type resolver and calculate offset to the existing
definition of a type abbreviation.

Local relocs use offset in the abbrev section of the containing
atom plus addend to generate a local relocation.
2022-06-06 19:58:51 +02:00
Jakub Konka
0cab01adbf elf: refactor and enhance logging symtab 2022-06-06 19:58:47 +02:00
Koakuma
97d35a5147 behaviortest: Skip 'align(N) on functions' on sparc64 for now 2022-06-06 21:17:09 +07:00
Koakuma
ec7f2a105f stage2: sparc64: Implement airPtrElemPtr 2022-06-06 21:17:09 +07:00
Koakuma
f6eb83c91c stage2: sparc64: Implement airArrayToSlice 2022-06-06 21:17:09 +07:00
BratishkaErik
1bdc2b777b tools: fix update-linux-headers.zig and process_headers.zig
Signed-off-by: BratishkaErik <bratishkaerik@getgoogleoff.me>
2022-06-06 15:53:53 +02:00
Koakuma
f87dd285bb stage2: sparc64: binOp/mul: Use template from add 2022-06-06 20:34:53 +07:00
Koakuma
31f24dbc55 stage2: sparc64: Implement airWrapErrUnionErr 2022-06-06 20:34:53 +07:00
Koakuma
c00d493a00 stage2: sparc64: Add some notes about stack space allocation 2022-06-06 20:34:53 +07:00
Koakuma
5d61f32887 stage2: sparc64: Implement airSlice 2022-06-06 20:34:53 +07:00
Koakuma
8b70abfcc6 stage2: sparc64: Fix & optimize 64-bit truncRegister 2022-06-06 20:34:53 +07:00
Koakuma
4d50e52c37 stage2: sparc64: Implement SPARCv9 xor, xnor, & not 2022-06-06 20:34:53 +07:00
Koakuma
97f9bf7e90 stage2: sparc64: Add BPr relocation to performReloc 2022-06-06 20:34:53 +07:00
Koakuma
23150de9c4 stage2: sparc64: Implement airNot 2022-06-06 20:34:53 +07:00
Koakuma
9ad74b6087 stage2: sparc64: Implement SPARCv9 addcc and movcc 2022-06-06 20:34:53 +07:00
Koakuma
97c43afefe stage2: sparc64: Spill CCR before doing calls 2022-06-06 20:34:53 +07:00
Koakuma
2dfe307d60 stage2: sparc64: Some bookkeeping fixes 2022-06-06 20:34:53 +07:00
Koakuma
89b4195c69 stage2: sparc64: Account for delay slot in airBlock 2022-06-06 20:34:53 +07:00
Koakuma
3220e0b61c stage2: sparc64: Proper handling of compare flags 2022-06-06 20:34:53 +07:00
Koakuma
9db81fee5d stage2: sparc64: Implement airStructFieldVal 2022-06-06 20:34:53 +07:00
Koakuma
3d662cfaf4 stage2: sparc64: Implement airAddSubOverflow 2022-06-06 20:34:53 +07:00
Koakuma
093332c02e stage2: sparc64: Implement condition code spilling 2022-06-06 20:34:53 +07:00
Koakuma
38aa431e03 stage2: sparc64: Fix CompareOperator <-> ICondition mapping 2022-06-06 20:34:52 +07:00
joachimschmidt557
a34f3ff04a
stage2 ARM: implement try AIR instruction 2022-06-06 14:22:40 +02:00
Gregory Anders
135b91aecd
Treat blocks with "return" as "noreturn"
Block statements that end with "break" should not be considered
"noreturn" for the enclosing scope, but other "noreturn" instructions
(return, panic, compile error, etc.) should be. This differentiation
necessitates handling "break" differently from the other "noreturn"
instructions when inside a block statement.
2022-06-06 13:13:52 +03:00
Jakub Konka
5dade176d8 sema: set new Decl alignment to 0 for generic call instantiation 2022-06-05 17:31:22 +02:00
Jakub Konka
95966f6fd7 elf+macho: use explicit alignment on decl is specified 2022-06-05 16:46:50 +02:00
Jakub Konka
ff00bbf4de x64: lower try and try_ptr 2022-06-05 10:37:08 +02:00
Andrew Kelley
6da420419d Sema: avoid emitting unused is_non_err AIR instruction 2022-06-05 10:37:08 +02:00
Andrew Kelley
d2f31d315e C backend: implement try instruction 2022-06-05 10:37:08 +02:00
Luuk de Gram
779770cff5 wasm: Implement try instruction 2022-06-05 10:37:08 +02:00
Andrew Kelley
f4ac37f55d Sema: extract out zirTryPtr from zirTry
This function took is_ptr: bool and then branched on it three times.
Now, instead, each implementation does no branching and the logic is
easier to follow, both for maintainers and compilers.

I also fixed a bug with TryPtr not ensuring enough capacity in the extra
array.
2022-06-05 10:37:08 +02:00
Andrew Kelley
6d3586e0ed explicit "_ptr" variants of ZIR try instruction
* Introduce "_ptr" variants of ZIR try instruction to disallow constructs
   such as `try` on a pointer value instead of an error union value.
 * Disable the "_inline" variants of the ZIR try instruction for now because
   we are out of ZIR tags. I will free up some space in an independent commit.
 * AstGen: fix tryExpr calling rvalue() on ResultLoc.ref
2022-06-05 10:37:08 +02:00
Andrew Kelley
00720c52f6 Sema: implement try_inline 2022-06-05 10:37:08 +02:00
Andrew Kelley
ef885a78d6 stage2: implement the new "try" ZIR/AIR instruction
Implements semantic analysis for the new try/try_inline ZIR
instruction. Adds the new try/try_ptr AIR instructions and implements
them for the LLVM backend.

Fixes not calling rvalue() for tryExpr in AstGen.

This is part of an effort to implement #11772.
2022-06-05 10:37:08 +02:00
Andrew Kelley
0224ad19b8 AstGen: introduce try instruction
This introduces two ZIR instructions:
 * `try`
 * `try_inline`

This is part of an effort to implement #11772.
2022-06-05 10:37:08 +02:00
Jakub Konka
33826a6a2e x64: disable misbehaving behavior tests 2022-06-05 10:36:54 +02:00
Jakub Konka
1b5dd4e148
Merge pull request #11790 from joachimschmidt557/stage2-arm
stage2 ARM: implement basic switch expressions
2022-06-05 09:10:12 +02:00
Andrew Kelley
43db697b46
Merge pull request #11789 from Vexu/stage2
Stage2 fixes towards `zig2 build test-std` working
2022-06-04 16:29:26 -04:00
joachimschmidt557
d5ee451177
stage2 ARM: introduce support for basic switch expressions 2022-06-04 19:58:34 +02:00
Veikka Tuominen
50a6b0f3ac Sema: fix function type callconv inference 2022-06-04 11:33:18 +03:00
Veikka Tuominen
6d44c0a16c std: update tests to stage2 semantics 2022-06-03 20:21:20 +03:00
Veikka Tuominen
1a7b4ddeae std: disable tests that crash stage2 2022-06-03 20:21:20 +03:00