stage2: sparc64: Fix & optimize 64-bit truncRegister

2026-02-21 16:54:52 +00:00 · 2022-06-01 19:32:14 +07:00 · 2022-06-01 19:32:14 +07:00 · 8b70abfcc6
commit 8b70abfcc6
parent 4d50e52c37
1 changed files with 3 additions and 1 deletions
--- a/src/arch/sparc64/CodeGen.zig
+++ b/src/arch/sparc64/CodeGen.zig
@ -3569,11 +3569,13 @@ fn truncRegister(
            });
        },
        64 => {
+            if (dest_reg == operand_reg)
+                return; // Copy register to itself; nothing to do.
            _ = try self.addInst(.{
                .tag = .mov,
                .data = .{
                    .arithmetic_2op = .{
-                        .is_imm = true,
+                        .is_imm = false,
                        .rs1 = dest_reg,
                        .rs2_or_imm = .{ .rs2 = operand_reg },
                    },