9840 Commits

Author SHA1 Message Date
Jakub Konka
6a65561e3e
Merge pull request #19958 from ziglang/macho-check-object
Step.CheckObject: add support for dumping raw section contents for MachO
2024-05-14 07:11:41 +02:00
Jakub Konka
2d537da6bd Step.CheckObject: support dumping raw section contents for MachO 2024-05-13 09:14:35 +02:00
Jakub Konka
5d619da2de Step.CheckObject: put MachO object parsing logic in ObjectContext wrapper 2024-05-13 08:56:15 +02:00
Andrew Kelley
e2ec54bb38
Merge pull request #19926 from squeek502/windows-sdk-cachepath-registry
WindowsSdk: Fix finding the _Instances directory when it's not in the default location
2024-05-12 09:39:13 -04:00
Ronald Chen
c77afca957 [std] Fixed bug missing optional for lpName param on CreateEventExW. fixes #19946
https://learn.microsoft.com/en-us/windows/win32/api/synchapi/nf-synchapi-createeventexw
2024-05-12 07:45:40 +02:00
Georgijs
084c2cd90f
windows: use permissive file share flags everywhere (#19505)
* use permissive file share flags everywhere

* remove file_share_delete from createnamedpipefile
2024-05-11 23:34:40 +02:00
Jakub Konka
86d8688c7f
Merge pull request #19431 from Rexicon226/revive-riscv
revive STAGE2 RISCV64 backend
2024-05-11 21:35:18 +02:00
Andrew Kelley
661a9be66b std.Build.Step.Run: add missing call to writeManifest
fixes #19938
2024-05-11 06:28:45 -07:00
David Rubin
ffb63a05a3 riscv: finally fix bug + airAggregateInit
i just hadn't realized that I placed the `riscv_start` branch in the non-simplified
starts
2024-05-11 02:17:24 -07:00
David Rubin
d9e0cafe64 riscv: add stage2_riscv to test matrix and bypass failing tests 2024-05-11 02:17:24 -07:00
David Rubin
e622485df8 riscv: actually working test runner 2024-05-11 02:17:11 -07:00
David Rubin
d19b77d63f riscv: back to hello world panics 2024-05-11 02:17:11 -07:00
David Rubin
6740c1f084 riscv: big rewrite to use latest liveness
this one is even harder to document then the last large overhaul.

TLDR;
- split apart Emit.zig into an Emit.zig and a Lower.zig
- created seperate files for the encoding, and now adding a new instruction
is as simple as just adding it to a couple of switch statements and providing the encoding.
- relocs are handled in a more sane maner, and we have a clear defining boundary between
lea_symbol and load_symbol now.
- a lot of different abstractions for things like the stack, memory, registers, and others.
- we're using x86_64's FrameIndex now, which simplifies a lot of the tougher design process.
- a lot more that I don't have the energy to document. at this point, just read the commit itself :p
2024-05-11 02:17:11 -07:00
David Rubin
8ac239ebce riscv: add enough components to get a test runner working 2024-05-11 02:17:11 -07:00
David Rubin
3bf008a3d0 riscv: implement slices 2024-05-11 02:17:11 -07:00
David Rubin
350ad90cee riscv: totally rewrite how we do loads and stores
this commit is a little too large to document fully, however the main gist of it this

- finish the `genInlineMemcpy` implement
- rename `setValue` to `genCopy` as I agree with jacob that it's a better name
- add in `genVarDbgInfo` for a better gdb experience
- follow the x86_64's method for genCall, as the procedure is very similar for us
- add `airSliceLen` as it's trivial
- change up the `airAddWithOverflow implementation a bit
- make sure to not spill of the elem_ty is 0 size
- correctly follow the RISC-V calling convention and spill the used calle saved registers in the prologue
and restore them in the epilogue
- add `address`, `deref`, and `offset` helper functions for MCValue. I must say I love these,
they make the code very readable and super verbose :)
- fix a `register_manager.zig` issue where when using the last register in the set, the value would overflow at comptime.
was happening because we were adding to `max_id` before subtracting from it.
2024-05-11 02:17:11 -07:00
David Rubin
cbf62bd6dc riscv: switch default_panic to use the message 2024-05-11 02:17:11 -07:00
David Rubin
685f828218 riscv: add a custom panic function
this provides a much better indication of when we are having a controlled panic with an error message
or when we are actually segfaulting, as before the `trap` as causing a segfault.
2024-05-11 02:17:11 -07:00
David Rubin
63bbf66553 riscv: remove an allocation from dwarf.zig 2024-05-11 02:17:11 -07:00
David Rubin
3ccf0fd4c2 riscv: basic struct field access
the current implementation only works when the struct is in a register. we use some shifting magic
to get the field into the LSB, and from there, given the type provenance, the generated code should
never reach into the bits beyond the bit size of the type and interact with the rest of the struct.
2024-05-11 02:17:11 -07:00
David Rubin
2be3033acd riscv: implement basic branching
we use a code offset map in Emit.zig to pre-compute what byte offset each MIR instruction is at. this is important because they can be
of different size
2024-05-11 02:17:11 -07:00
David Rubin
28df64cba4 riscv: implement @abs
- add the `abs` MIR instruction
- implement `@abs` by shifting to the right by `bits - 1`, and xoring.
2024-05-11 02:17:11 -07:00
David Rubin
060c475fcd riscv: update start.zig and restore ra from the proper stack offset 2024-05-11 02:17:11 -07:00
David Rubin
dceff2592f riscv: initial cleanup and work 2024-05-11 02:17:11 -07:00
Dominic
1550b5b16d
astgen: fix result info for catch switch_block_err_union 2024-05-11 12:06:13 +03:00
190n
cc39ce28a1
Do not run asserts for WASI alignment when not targeting WASI 2024-05-11 07:23:07 +00:00
Lucas Santos
f71f27bcb0 Avoid unnecessary operation in PageAllocator.
There's no need to call `alignForward` before `VirtualAlloc`.
From [MSDN](https://learn.microsoft.com/en-us/windows/win32/api/memoryapi/nf-memoryapi-virtualalloc):
```
If the lpAddress parameter is NULL, this value is rounded up to the next page boundary
```
2024-05-10 22:51:52 +03:00
Abhinav Gupta
fe1b397606
ChildProcess: document StdIo behaviors (#17553)
Add some basic documentation for the different ChildProcess.StdIo
behaviors and the fields they affect.
2024-05-10 14:05:20 +00:00
expikr
841bb0a1fd
std.os.windows: add compileError warning against TCHAR & their corresponding string/pointer types (#18741) 2024-05-10 07:48:05 +00:00
Veikka Tuominen
c4e3a49898 define an error set for std.io.tty.Config.setColor 2024-05-10 10:29:16 +03:00
Ryan Liptak
cdc0cee135 WindowsSdk: Fix every registry key being opened with KEY_WOW64_32KEY
Now, an options struct is used to determine whether or not KEY_WOW64_32KEY should be set when opening a registry key.
2024-05-09 23:15:18 -07:00
Ryan Liptak
cf8f0cdae9 WindowsSdk: Fix finding the _Instances directory when it's not in the default location
Information about installed MSVC instances are stored in `state.json` files within a `Packages/_Instances` directory. The default location for this is `%PROGRAMDATA%\Microsoft\VisualStudio\Packages\_Instances`. However, it is possible for the Packages directory to be put somewhere else. In that case, the registry value `HKLM\SOFTWARE\Microsoft\VisualStudio\Setup\CachePath` is set and contains the path to the Packages directory.

Previously, WindowsSdk did not check that registry value. After this commit, the registry value `HKLM\SOFTWARE\Microsoft\VisualStudio\Setup\CachePath` is checked first, which matches what ISetupEnumInstances does (according to a Procmon log).
2024-05-09 22:22:41 -07:00
Garfield Lee
e69caaa39f
lib/std/os/windows/kernel32: add signature for SetConsoleMode (#18715)
- From lib/libc/include/any-windows-any/wincon.h#L235
- See also https://learn.microsoft.com/en-us/windows/console/setconsolemode
- Also add DISABLE_NEWLINE_AUTO_RETURN constant which will be used by SetConsoleMode in lib/std/os/windows.

Co-authored-by: Kexy Biscuit <kexybiscuit@biscuitt.in>
2024-05-09 16:38:39 -07:00
Karl Bohlmark
6eb17a034a fix integer overflow in IoUring buffer ring size calculation 2024-05-09 16:00:01 -07:00
Pavel Verigo
d4d1efeb3e std.compress.flate: fix panic when reading into empty buffer 2024-05-09 15:51:42 -07:00
Andrew Kelley
68629fedef
Merge pull request #19918 from ziglang/xros
Add support for VisionOS
2024-05-09 15:45:42 -07:00
february cozzocrea
c9ad1b5199 aro translate-c: support for record types added 2024-05-09 13:46:50 -07:00
Jakub Konka
2e1fc0dd14 handle visionos target OS tag in the compiler
* rename .xros to .visionos as agreed in the tracking issue
* add support for VisionOS platform in the MachO linker
2024-05-09 15:04:15 +02:00
Andrew Kelley
98a30acad6 libcxxabi patch: respect NDEBUG
zig patch: respect NDEBUG. Otherwise the file path makes it into the
binary, causing non-reproducible builds.
2024-05-08 19:37:30 -07:00
Andrew Kelley
e89d6fc503 fix wrong int alignment for i65..i127 on x86 arch 2024-05-08 19:37:30 -07:00
Andrew Kelley
126c9a34af restructure unit test to be easier to debug 2024-05-08 19:37:29 -07:00
Andrew Kelley
0b31e2ab27 std.Target: add spirv to toCoffTarget 2024-05-08 19:37:29 -07:00
Andrew Kelley
b7799ef322 std.Target.maxIntAlignment: move to compiler implementation
This should not be a public API, and the x86 backend does not support
the value 16.
2024-05-08 19:37:29 -07:00
Andrew Kelley
f6f0fefd8b libc++: patch tz impl to crash on windows instead of FTBFS 2024-05-08 19:37:29 -07:00
Andrew Kelley
3c21db6392 update detectAMDProcessor to detect znver4 2024-05-08 19:37:29 -07:00
Andrew Kelley
06ee65af9e libcxx: update to LLVM 18
release/18.x branch, commit 78b99c73ee4b96fe9ce0e294d4632326afb2db42

This adds the flag `-D_LIBCPP_HARDENING_MODE` which is determined based
on the Zig optimization mode.

This commit also fixes libunwind, libcxx, and libcxxabi to properly
report sub compilation errors.
2024-05-08 19:37:29 -07:00
Andrew Kelley
bc6ebc6f25 libcxxabi: update to LLVM 18
release/18.x branch, commit 78b99c73ee4b96fe9ce0e294d4632326afb2db42
2024-05-08 19:37:29 -07:00
Andrew Kelley
6295415da7 libunwind: update to LLVM 18
release/18.x branch, commit 78b99c73ee4b96fe9ce0e294d4632326afb2db42
2024-05-08 19:37:29 -07:00
Andrew Kelley
a6856ef6d2 LLVM 18 uses 16 byte alignment for x86_64 i128 2024-05-08 19:37:28 -07:00
Andrew Kelley
d34fae26d5 LLVM 18 std lib updates and fixes
* some manual fixes to generated CPU features code. In the future it
  would be nice to make the script do those automatically.

* add to various target OS switches. Some of the values I was unsure of
  and added TODO panics, for example in the case of spirv CPU arch.
2024-05-08 19:37:28 -07:00