111 Commits

Author SHA1 Message Date
Veikka Tuominen
0a7be71bc2
stage2 cbe: non pointer optionals 2021-03-08 00:33:56 +02:00
Veikka Tuominen
cfc19eace7
stage2 cbe: errors 2021-03-08 00:33:07 +02:00
Veikka Tuominen
c22f010fdd
stage2 cbe: regular optional types 2021-03-08 00:33:07 +02:00
Veikka Tuominen
ca20d0ea26
stage2 cbe: pointer like optionals 2021-03-08 00:32:52 +02:00
Veikka Tuominen
8c6e7fb2c7
stage2: implement var args 2021-03-06 15:55:29 +02:00
Timon Kruiper
d4ec0279d3 stage2: add support for optionals in the LLVM backend
We can now codegen optionals! This includes the following instructions:
- is_null
- is_null_ptr
- is_non_null
- is_non_null_ptr
- optional_payload
- optional_payload_ptr
- br_void

Also includes a test for optionals.
2021-03-02 19:02:55 -07:00
Andrew Kelley
449f4de382 zig fmt src/ 2021-02-24 21:54:23 -07:00
Andrew Kelley
8e6c2b7a47 Merge remote-tracking branch 'origin/master' into ast-memory-layout 2021-02-24 15:08:23 -07:00
Veikka Tuominen
ef6aa3d027
Merge pull request #7960 from Luukdegram/wasm-extern
stage2: Add support for extern functions for the wasm backend
2021-02-21 12:22:01 +02:00
Isaac Freund
070e548acf
std: remove io.AutoIndentingStream
This type is not widely applicable enough to be a public part of the
public interface of the std.

The current implementation in only fully utilized by the zig fmt
implementation, which could benefit by even tighter integration as
will be demonstrated in the next commit. Therefore, move the current
io.AutoIndentingStream to lib/std/zig/render.zig.

The C backend of the self hosted compiler also use this type currently,
but it does not require anywhere near its full complexity. Therefore,
implement a greatly simplified version of this interface in
src/codegen/c.zig.
2021-02-16 23:20:46 +01:00
joachimschmidt557
c2beaba85a stage2 ARM: fix callee_preserved_regs
Previously, the registers included r0, r1, r2, r3 which are not
included in the callee saved registers according to the Procedure Call
Standard for the ARM Architecture.
2021-02-09 23:57:43 +01:00
Luuk de Gram
36df6a008f
Ensure function indices are correct and fix a memory leak 2021-02-05 18:06:25 +01:00
Luuk de Gram
aa3e0ff454
Create type declarations for extern functions and write the 'import' section 2021-02-05 18:06:20 +01:00
Andrew Kelley
102d954220
Merge pull request #7827 from Snektron/spirv-setup
Stage 2: SPIR-V setup
2021-02-01 12:49:51 -08:00
Andrew Kelley
1517ed0a5e
Merge pull request #7895 from Luukdegram/wasm-control-flow
stage2: wasm control flow
2021-02-01 12:29:22 -08:00
Veikka Tuominen
75acfcf0ea
stage2: reimplement switch 2021-02-01 15:45:11 +02:00
Veikka Tuominen
3ec5c9a3bc
stage2 cbe: implement not and some bitwise ops 2021-02-01 08:48:24 +02:00
Veikka Tuominen
106520329e
stage2 cbe: implement switchbr 2021-02-01 08:48:22 +02:00
Veikka Tuominen
258f3ec5ec
stage2 cbe: block results 2021-02-01 08:47:25 +02:00
Veikka Tuominen
bdfe3aeab8
stage2 cbe: condbr and breaks 2021-02-01 08:47:25 +02:00
Veikka Tuominen
6ca0ff90b6
stage2 cbe: use AutoIndentingStream 2021-02-01 08:47:25 +02:00
Veikka Tuominen
81c512f35b
stage2 cbe: loop instruction 2021-02-01 08:47:25 +02:00
Luuk de Gram
cc46c1b902
Add tests, fix locals that are created in blocks like loops, and handle all breaks correctly 2021-01-26 19:47:15 +01:00
Andrew Kelley
4ca1f4ec2e
Merge pull request #7846 from LemonBoy/filtertest
stage1: don't filter test blocks with empty label
2021-01-25 10:39:11 -08:00
Luuk de Gram
a0d81caec9
Nested conditions and loops support 2021-01-24 14:38:35 +01:00
Andrew Kelley
0d4b6ac741 add LTO support
The CLI gains -flto and -fno-lto options to override the default.
However, the cool thing about this is that the defaults are great! In
general when you use build-exe in release mode, Zig will enable LTO if
it would work and it would help.

zig cc supports detecting and honoring the -flto and -fno-lto flags as
well. The linkWithLld functions are improved to all be the same with
regards to copying the artifact instead of trying to pass single objects
through LLD with -r. There is possibly a future improvement here as
well; see the respective TODOs.

stage1 is updated to support outputting LLVM bitcode instead of machine
code when lto is enabled. This allows LLVM to optimize across the Zig and
C/C++ code boundary.

closes #2845
2021-01-23 18:18:07 -07:00
LemonBoy
134f5fd3d6 std: Update test "" to test where it makes sense 2021-01-22 15:46:58 +01:00
Robin Voetter
1055344673 SPIR-V: Use free list for result id generation 2021-01-19 15:28:17 +01:00
Robin Voetter
801732aebd SPIR-V: OpMemoryModel and basic capability generation 2021-01-19 15:28:17 +01:00
Robin Voetter
71ac82ecb0 SPIR-V: Make emitting binary more efficient 2021-01-19 15:28:17 +01:00
Robin Voetter
02c138fe70 SPIR-V: Add glsl450 and vulkan spir-v operating system definitions 2021-01-19 15:28:17 +01:00
Robin Voetter
b2b87b5900 SPIR-V: Linking and codegen setup 2021-01-19 15:28:17 +01:00
Robin Voetter
9a6babf482 SPIR-V: Add generated specification 2021-01-19 15:28:17 +01:00
Andrew Kelley
1a05b54520 update wasm backend to match new Module API
Fixes a logical merge conflict that I didn't notice before.
2021-01-18 14:12:05 -07:00
Andrew Kelley
46dd058d59
Merge pull request #7797 from Luukdegram/wasm-refactor
stage2: wasm - Refactor codegen for wasm similar to other backends
2021-01-18 12:35:52 -08:00
joachimschmidt557
ea6f3e3fd1
stage2 AArch64: add add/subtract (immediate) instructions 2021-01-17 22:40:14 +01:00
Jakub Konka
b25cf7db02 stage2 aarch64: add basic function pro/epilogue
Fix typo in `nop` implementation.
Simplify `aarch64` macOS tests.
2021-01-17 14:57:53 +01:00
Andrew Kelley
8c9ac4db97 stage2: implement error notes and regress -femit-zir
* Implement error notes
   - note: other symbol exported here
   - note: previous else prong is here
   - note: previous '_' prong is here
 * Add Compilation.CObject.ErrorMsg. This object properly converts to
   AllErrors.Message when the time comes.
 * Add Compilation.CObject.failure_retryable. Properly handles
   out-of-memory and other transient failures.
 * Introduce Module.SrcLoc which has not only a byte offset but also
   references the file which the byte offset applies to.
 * Scope.Block now contains both a pointer to the "owner" Decl and the
   "source" Decl. As an example, during inline function call, the
   "owner" will be the Decl of the caller and the "source" will be the
   Decl of the callee.
 * Module.ErrorMsg now sports a `file_scope` field so that notes can
   refer to source locations in a file other than the parent error
   message.
 * Some instances where a `*Scope` was stored, now store a
   `*Scope.Container`.
 * Some methods in the `Scope` namespace were moved to the more specific
   type, since there was only an implementation for one particular tag.
   - `removeDecl` moved to `Scope.Container`
   - `destroy` moved to `Scope.File`
 * Two kinds of Scope deleted:
   - zir_module
   - decl
 * astgen: properly use DeclVal / DeclRef. DeclVal was incorrectly
   changed to be a reference; this commit fixes it. Fewer ZIR
   instructions processed as a result.
   - declval_in_module is renamed to declval
   - previous declval ZIR instruction is deleted; it was only for .zir
     files.
 * Test harness: friendlier diagnostics when an unexpected set of errors
   is encountered.
 * zir_sema: fix analyzeInstBlockFlat by properly calling resolvingInst
   on the last zir instruction in the block.

Compile log implementation:
 * Write to a buffer rather than directly to stderr.
 * Only keep track of 1 callsite per Decl.
 * No longer mutate the ZIR Inst struct data.
 * "Compile log statement found" errors are only emitted when there are
   no other compile errors.

-femit-zir and support for .zir source files is regressed. If we wanted
to support this again, outputting .zir would need to be done as yet
another backend rather than in the haphazard way it was previously
implemented.

For parsing .zir, it was implemented previously in a way that was not
helpful for debugging. We need tighter integration with the test harness
for it to be useful; so clearly a rewrite is needed. Given that a
rewrite is needed, and it was getting in the way of progress and
organization of the rest of stage2, I regressed the feature.
2021-01-16 22:51:01 -07:00
joachimschmidt557
d2a297c2b3 stage2 ARM: add extra load/store instructions 2021-01-16 12:06:31 -08:00
joachimschmidt557
fbd5fbe729 stage2 AArch64: add very basic return values 2021-01-16 12:05:38 -08:00
Luuk de Gram
6a87ce0b62
Generate correct opcode for 'addGen' depending on type 2021-01-16 18:22:20 +01:00
Luuk de Gram
6c19aeddca
Add tests and move tests to wasm's own file 2021-01-16 14:58:04 +01:00
Luuk de Gram
4b2538f72c
Cleanup and 'add' instruction for bigger test area 2021-01-15 23:27:38 +01:00
Luuk de Gram
bb74f72e97
stage2: refactor wasm backend - similar to the other backends 2021-01-15 23:27:38 +01:00
Timon Kruiper
e1d8073d2f stage2: add support for loops in LLVM backend
A simple `while(true) {}` loop generates the following LLVMIR:
```
define i32 @main() {
Entry:
  br label %Loop

Loop:                                 ; preds = %Loop, %Entry
  br label %Loop
}
```

Also implement TZIR printing for loops and add a corresponding test.
2021-01-10 17:47:34 -08:00
Andrew Kelley
5c49a137d5
Merge pull request #7725 from FireFox317/even-more-llvm
stage2: initial implementation of control flow in LLVM backend + TZIR printing
2021-01-09 12:32:10 -08:00
Timon Kruiper
56c059077c stage2: add initial impl of control flow in LLVM backend
The following TZIR instrutions have been implemented in the backend:
- all cmp operators (lt, lte, gt, gte, eq, neq)
- block
- br
- condbr

The following LLVMIR is generated for a simple assert function:
```
define void @assert(i1 %0) {
Entry:
  %1 = alloca i1, align 1
  store i1 %0, i1* %1, align 1
  %2 = load i1, i1* %1, align 1
  %3 = xor i1 %2, true
  br i1 %3, label %Then, label %Else

Then:                                             ; preds = %Entry
  call void @llvm.debugtrap()
  unreachable

Else:                                             ; preds = %Entry
  br label %Block

Block:                                            ; preds = %Else
  ret void
}
```

See tests for more examples.
2021-01-08 19:30:52 +01:00
Jonathan Marler
31802c6c68 remove z/Z format specifiers
Zig's format system is flexible enough to add custom formatters.  This PR removes the new z/Z format specifiers that were added for printing Zig identifiers and replaces them with custom formatters.
2021-01-07 23:49:22 -08:00
Jay Petacat
a9b505fa77 Reduce use of deprecated IO types
Related: #4917
2021-01-07 23:48:58 -08:00
Andrew Kelley
76870a2265
Merge pull request #7700 from FireFox317/more-stage2-stuff-llvm
stage2: improvements to LLVM backend
2021-01-06 16:06:32 -08:00