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stage2 ARM: add extra load/store instructions
This commit is contained in:
joachimschmidt557
Andrew Kelley
parent
fbd5fbe729
commit
d2a297c2b3
@ -2630,21 +2630,34 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.register => |reg| {
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const abi_size = ty.abiSize(self.target.*);
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const adj_off = stack_offset + abi_size;
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const offset = if (adj_off <= math.maxInt(u12)) blk: {
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break :blk Instruction.Offset.imm(@intCast(u12, adj_off));
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} else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0);
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switch (abi_size) {
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1 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.strb(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32()),
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2 => return self.fail(src, "TODO implement strh", .{}),
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4 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.str(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32()),
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else => return self.fail(src, "TODO a type of size {} is not allowed in a register", .{abi_size}),
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1, 4 => {
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const offset = if (adj_off <= math.maxInt(u12)) blk: {
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break :blk Instruction.Offset.imm(@intCast(u12, adj_off));
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} else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0);
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const str = switch (abi_size) {
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1 => Instruction.strb,
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4 => Instruction.str,
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else => unreachable,
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};
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writeInt(u32, try self.code.addManyAsArray(4), str(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32());
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},
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2 => {
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const offset = if (adj_off <= math.maxInt(u8)) blk: {
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break :blk Instruction.ExtraLoadStoreOffset.imm(@intCast(u8, adj_off));
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} else Instruction.ExtraLoadStoreOffset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }));
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.strh(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32());
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},
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else => return self.fail(src, "TODO implement storing other types abi_size={}", .{abi_size}),
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}
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},
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.memory => |vaddr| {
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@ -2836,20 +2849,33 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// const abi_size = ty.abiSize(self.target.*);
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const abi_size = 4;
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const adj_off = unadjusted_off + abi_size;
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const offset = if (adj_off <= math.maxInt(u12)) blk: {
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break :blk Instruction.Offset.imm(@intCast(u12, adj_off));
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} else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0);
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switch (abi_size) {
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1 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldrb(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32()),
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2 => return self.fail(src, "TODO implement ldrh", .{}),
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4 => writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32()),
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1, 4 => {
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const offset = if (adj_off <= math.maxInt(u12)) blk: {
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break :blk Instruction.Offset.imm(@intCast(u12, adj_off));
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} else Instruction.Offset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }), 0);
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const ldr = switch (abi_size) {
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1 => Instruction.ldrb,
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4 => Instruction.ldr,
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else => unreachable,
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};
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writeInt(u32, try self.code.addManyAsArray(4), ldr(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32());
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},
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2 => {
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const offset = if (adj_off <= math.maxInt(u8)) blk: {
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break :blk Instruction.ExtraLoadStoreOffset.imm(@intCast(u8, adj_off));
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} else Instruction.ExtraLoadStoreOffset.reg(try self.copyToTmpRegister(src, MCValue{ .immediate = adj_off }));
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writeInt(u32, try self.code.addManyAsArray(4), Instruction.ldrh(.al, reg, .fp, .{
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.offset = offset,
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.positive = false,
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}).toU32());
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},
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else => return self.fail(src, "TODO a type of size {} is not allowed in a register", .{abi_size}),
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}
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},
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@ -240,6 +240,22 @@ pub const Instruction = union(enum) {
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fixed: u2 = 0b01,
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cond: u4,
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},
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ExtraLoadStore: packed struct {
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imm4l: u4,
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fixed_1: u1 = 0b1,
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op2: u2,
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fixed_2: u1 = 0b1,
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imm4h: u4,
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rt: u4,
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rn: u4,
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o1: u1,
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write_back: u1,
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imm: u1,
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up_down: u1,
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pre_index: u1,
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fixed_3: u3 = 0b000,
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cond: u4,
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},
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BlockDataTransfer: packed struct {
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register_list: u16,
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rn: u4,
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@ -468,6 +484,29 @@ pub const Instruction = union(enum) {
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}
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};
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/// Represents the offset operand of an extra load or store
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/// instruction.
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pub const ExtraLoadStoreOffset = union(enum) {
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immediate: u8,
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register: u4,
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pub const none = ExtraLoadStoreOffset{
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.immediate = 0,
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};
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pub fn reg(register: Register) ExtraLoadStoreOffset {
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return ExtraLoadStoreOffset{
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.register = register.id(),
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};
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}
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pub fn imm(immediate: u8) ExtraLoadStoreOffset {
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return ExtraLoadStoreOffset{
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.immediate = immediate,
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};
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}
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};
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/// Represents the register list operand to a block data transfer
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/// instruction
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pub const RegisterList = packed struct {
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@ -495,6 +534,7 @@ pub const Instruction = union(enum) {
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.Multiply => |v| @bitCast(u32, v),
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.MultiplyLong => |v| @bitCast(u32, v),
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.SingleDataTransfer => |v| @bitCast(u32, v),
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.ExtraLoadStore => |v| @bitCast(u32, v),
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.BlockDataTransfer => |v| @bitCast(u32, v),
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.Branch => |v| @bitCast(u32, v),
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.BranchExchange => |v| @bitCast(u32, v),
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@ -617,6 +657,43 @@ pub const Instruction = union(enum) {
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};
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}
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fn extraLoadStore(
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cond: Condition,
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pre_index: bool,
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positive: bool,
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write_back: bool,
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o1: u1,
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op2: u2,
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rn: Register,
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rt: Register,
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offset: ExtraLoadStoreOffset,
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) Instruction {
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const imm4l: u4 = switch (offset) {
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.immediate => |imm| @truncate(u4, imm),
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.register => |reg| reg,
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};
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const imm4h: u4 = switch (offset) {
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.immediate => |imm| @truncate(u4, imm >> 4),
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.register => |reg| 0b0000,
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};
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return Instruction{
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.ExtraLoadStore = .{
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.imm4l = imm4l,
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.op2 = op2,
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.imm4h = imm4h,
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.rt = rt.id(),
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.rn = rn.id(),
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.o1 = o1,
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.write_back = @boolToInt(write_back),
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.imm = @boolToInt(offset == .immediate),
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.up_down = @boolToInt(positive),
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.pre_index = @boolToInt(pre_index),
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.cond = @enumToInt(cond),
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},
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};
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}
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fn blockDataTransfer(
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cond: Condition,
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rn: Register,
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@ -913,6 +990,23 @@ pub const Instruction = union(enum) {
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return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 1, args.write_back, 0);
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}
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// Extra load/store
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pub const ExtraLoadStoreOffsetArgs = struct {
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pre_index: bool = true,
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positive: bool = true,
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offset: ExtraLoadStoreOffset,
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write_back: bool = false,
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};
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pub fn strh(cond: Condition, rt: Register, rn: Register, args: ExtraLoadStoreOffsetArgs) Instruction {
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return extraLoadStore(cond, args.pre_index, args.positive, args.write_back, 0, 0b01, rn, rt, args.offset);
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}
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pub fn ldrh(cond: Condition, rt: Register, rn: Register, args: ExtraLoadStoreOffsetArgs) Instruction {
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return extraLoadStore(cond, args.pre_index, args.positive, args.write_back, 1, 0b01, rn, rt, args.offset);
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}
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// Block data transfer
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pub fn ldmda(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
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@ -1093,6 +1187,12 @@ test "serialize instructions" {
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}),
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.expected = 0b1110_01_0_1_1_0_0_0_0011_0000_000000000000,
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},
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.{ // strh r1, [r5]
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.inst = Instruction.strh(.al, .r1, .r5, .{
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.offset = Instruction.ExtraLoadStoreOffset.none,
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}),
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.expected = 0b1110_000_1_1_1_0_0_0101_0001_0000_1011_0000,
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},
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.{ // b #12
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.inst = Instruction.b(.al, 12),
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.expected = 0b1110_101_0_0000_0000_0000_0000_0000_0011,
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