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zig/src/codegen
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joachimschmidt557 c2beaba85a stage2 ARM: fix callee_preserved_regs 
Previously, the registers included r0, r1, r2, r3 which are not
included in the callee saved registers according to the Procedure Call
Standard for the ARM Architecture.
2021-02-09 23:57:43 +01:00
..
llvm
add LTO support
2021-01-23 18:18:07 -07:00
spirv
SPIR-V: Add generated specification
2021-01-19 15:28:17 +01:00
spu-mk2
rename src-self-hosted/ to src/
2020-09-21 18:38:55 -07:00
aarch64.zig
std: Update test "" to test where it makes sense
2021-01-22 15:46:58 +01:00
arm.zig
stage2 ARM: fix callee_preserved_regs
2021-02-09 23:57:43 +01:00
c.zig
stage2: reimplement switch
2021-02-01 15:45:11 +02:00
llvm.zig
SPIR-V: Add glsl450 and vulkan spir-v operating system definitions
2021-01-19 15:28:17 +01:00
riscv64.zig
rename src-self-hosted/ to src/
2020-09-21 18:38:55 -07:00
spirv.zig
SPIR-V: Use free list for result id generation
2021-01-19 15:28:17 +01:00
spu-mk2.zig
rename src-self-hosted/ to src/
2020-09-21 18:38:55 -07:00
wasm.zig
Add tests, fix locals that are created in blocks like loops, and handle all breaks correctly
2021-01-26 19:47:15 +01:00
x86_64.zig
rename src-self-hosted/ to src/
2020-09-21 18:38:55 -07:00
x86.zig
rename src-self-hosted/ to src/
2020-09-21 18:38:55 -07:00